Hello all,I've run into an unusual problem. I'll start off by describing my goal: I'm designing a circuit that can test for short circuits and open circuits in a wiring harness. The wiring harness does not have a CAN bus or anything complicated like that - just simple wires. Here's how it works I have two CPLDs, one as a designated driving end (all pins are output) and another as an receiving end (all pins are input). The driving end CPLD is programmed to be a Serial In Parallel Out shift register and the receiving end is a Parallel In Serial Out shift register. Let's assume all the wires in the harness are one-to-one i.e. no junctions. Let's also assume that there are only 8 wires. So, to test the first wire in the harness, the driving end register is loaded with 10000000. The receiving end also sees this and it all ends well. The driving end is then clocked and it reads 01000000. If the receiver also reads this, then that wire is OK. But suppose there is a short circuit between wire 2 and 3. If that's the case, then the receiving end will read 01100000. This, too, is OK as we have detected the short and can take action. But what happens at the driving end? The CPLD's pin 3 will be forcing 0V and pin 2 will be forcing 3.3V. The short circuit between pin 2 and 3 will result in two output pins connected together. I'm assume that a significant current will flow from pin 2 to pin 3 and damage could result. Note that the shift registers/CPLDs are being driven by a microcontroller. Also note that the harness is usually quite large, around 200-300 wires. Some of which are one-to-many connections. This is why a CPLD was an attractive option as it allows me to program a large shift register and allows testing of a large harness with a relatively small circuit. How can I handle such a problem?
The common solution is pulling up all wires with resistors and then drive the target line low with an open drain output.In the CPLD you'll program bidirectional I/Os. The data out signal should be hardwired to a low level and you control the output pin through the OE signal. If you don't want external resistors, you may use the internal pull up option, but I'd not recommend it if your wires are long: the built in pull ups are usually in the tens of kohm range and the signals can be affected by stray electrical noise.
If I understand your solution, it's as follows:Instead of outputting 01000000, I should instead output Z0ZZZZZZ, where Z symbolizes high impedance. The pull up resistors at the receiving end will then up the high impedance line to 3.3V. The receiver will therefore read: 10111111 If there is a short circuit between pin 2 and 3, then the receiver will read 10011111. But since the other pin is in high-impedance state, it will have no affect on the device. Do I understand you correctly? Regarding, internal pull up resistors. The Max V handbook states that min. value at 3.3V VCCIO is 5k. Will this not be adequate? If using external resistors provide more reliable resistors then I'll prefer those. However, I should mention that the speed of operation is not very high. The receiving end shift register is clocked at only 62.5kHz and I could reduce it further still. Naturally, the driving end is even slower. Do you still reckon that external resistors will provide us with a better option? If so, what value would you recommend? Secondly, what if I instead use pull down resistors? This would be beneficial as the current layout is only two layer and the bottom layer is a Ground. I could connect the resistors using only a via. Obviously, I will have to output Z1ZZZZZZ instead of Z0ZZZZZZ. Thank you for an excellent solution, by the way. Also, how would it handle an open wire? Here's my understanding, if suppose wire 4 is open. The driving end outputs ZZZ0ZZZZ. The receiver should read 11101111 but instead it reads 11111111. From this we know that we have an open circuit at pin 4. Am I correct?
--- Quote Start --- If I understand your solution, it's as follows: Instead of outputting 01000000, I should instead output Z0ZZZZZZ, where Z symbolizes high impedance. The pull up resistors at the receiving end will then up the high impedance line to 3.3V. The receiver will therefore read: 10111111 If there is a short circuit between pin 2 and 3, then the receiver will read 10011111. But since the other pin is in high-impedance state, it will have no affect on the device. Do I understand you correctly? --- Quote End --- Perfect. You got it. Regarding internal pull ups, the problem is that 5k is the minimum but the actual resistance is not controlled and will be very different on each device. I don't have the MaxV datasheet here, but I guess you can easily expect values up to 20k. Anyway if you are sure your wires won't catch up a lot of emi, internal pull ups are fine. I will not reduce the clock speed, but I'd rather exploit the higher than required speed to multiple sampling the received signals and perform a digital filtering: this way you should prevent receive errors even more.
Thank you very much. The wires are quite long - upto 1.5m and can be longer if they're meant for trucks. So they will indeed act as an antenna, I reckon.What value of resistance would you recommend in this case, for a pull down? Higher or lower than 5k?
I discussed this with my colleagues at work and they feel there a couple of limiting factors here. One of things that concern me is the fact most wiring harnesses are going to have some large junctions. Lets suppose we have two junctions with upto 20 wires going outward from both of them.If there is a short circuit between the junctions, the CPLD's pin will need to drive as much as 40 wires. With a 5K pull down resistor, the current from the pin will be about 0.66mA at 3.3V. If, however, there is a junction of 40 wires the current is about 26.4mA - which exceeds the Max V absolute max. ratings (which aren't continuos anyway!). Is the answer to this problem reducing the speed of operating and using a larger resistor? A 47K resistor and a 100 wire junction will lead to a current of just 7mA. OR - should I just use a transistor array IC at the output of the Max V and use those to drive the wires - in essence, a buffer?
Indeed the recommended solution would be using buffers. These will also help to protect CPLD pins from damage which is likely in case of such long wires possibly, shortcircuited and maybe subject to esd or other kind of electrical surges.I'd use a transistor array, pull up resistors <=10k and I'd design the test cycle in order to minimize errors due to electrical coupling or emi (i.e. for the 3rd wire, test both with 00100000 and with 11011111 pattern)
Would you recommend a MOSFET or a BJT array? I wonder whats the largest array I can get in an IC. One of the goals of the circuit is it should be able to test a harness of upto 300 or so wires.This is one of the reasons I'd prefer having a large array, but I'm not sure if they are available. A quick look at Newark and it seems MOSFET arrays are mostly just in Dual or Quad. For 300 wires, I'd end up needing 150 ICs. One solution to this problem is to forget 300 wires on a single board and instead have multiple boards. For instance, one board could be the "master board" and this can have the MCU and two Max V CPLDs. With a 144TQFP 5M240Z Max V, this board would be able to test 114 wires. This board require "only" 57 open drain ICs, if they have dual mosfet. And, in order to test more than 114 wires we can cascade more "daughter boards". A daughter board could contain just two Max V CPLDs, just like in the previous configuration minus the MCU. In essence, we'd have a cascaded shift register for both ends. Of course, the registers will need a SO pin so they can load bits on each clock cycle. What do you think of this approach? The advantage of this approach is, in some ways, less complexity and its also more cost effective. Most wiring harnesses don't have 300 wires! So why build a single large PCB when most of the harness are only going to require, suppose, 150 wires? I can't use a single massive BGA package because it's very hard to get it soldered locally, so we're sticking with 144TQFPs for now. Is it not possible to use the open drain outputs mentioned in the Max V Handbook? I read through it, but it seems the current is still limited by the IO pin. Plus I like the added benefit of protection for the CPLDs against damage when using buffers. EDIT: Just so I understand, you're suggesting that I should still drive the CPLD as we previously discussed i.e. use tri-state for outputs that are not active and 1 (or a 0) for the output that is. All lines should have a pull down (or pull up) resistor. All of this I understand - but how would the transistor connect to all this? Here's my attempt at understanding that part: The pull down resistor will be between the transistor's base and ground. When there nothing present on the line, the pull down resistor will have 0V on the base and the transistor will be OFF. When there is a 1 present on the line, the 3.3V will drop across the pull down resistor and the transistor will be on. We connect the harness' wire to the emitter of this transistor and its collector to Vcc. The wire's other end(s) are connected to to pins on the receiving end CPLD. Is this what you were suggesting? I apologize for so many questions! I'm just a bit lost on where to go with this.
Thanks a lot for the schematic. That helped clear things up. I assume I should connect the other end of the harness directly?EDIT: Also, I assume that this MOSFET should be located near the receiving end?
The schematic wdshen posted is corrrect. This is what I meant.MOSFET or BJT doesn't make a great difference nowadays in this configuration, provided you select them correctly, in particular the specification on maximum current. --- Quote Start --- I assume I should connect the other end of the harness directly? EDIT: Also, I assume that this MOSFET should be located near the receiving end? --- Quote End --- No! The buffer must be placed at the transmitting end, just outside fpga; unless it wouldn't make sense, since you'll have the fpga pin still driving the long wire. I'd neither connect the receiving side directly to fpga, for similar reasons; I'd place a buffer here, too. Using buffered lines allows you to use a higher voltage for testing the harness, thus improving emi immunity.
Thanks, Cris.Here's what I came up with, as a whole. The MOSFET on the left hand side is for the transmitting end and the MOSFET on the right for receiving. The wire connecting the MOSFETs is our wiring thats to be tested and the output from the right MOSFET is connected to the CPLD - hence, its Drain is at 3.3V. http://i.imgur.com/PFuDZ.png My only issue is that I will end up with a lot of transistors on the board due to this. But if you feel this is the best solution, I'll go with it. But suppose I also want a reasonable current to flow through the harness, how would change this circuit? As it stands, the current will be very low because of the high input resistance of MOSFETs.
--- Quote Start --- But suppose I also want a reasonable current to flow through the harness, how would change this circuit? As it stands, the current will be very low because of the high input resistance of MOSFETs. --- Quote End --- Simply move to to the receiver end the resistor which pulls up to +12V. Leave on driver end only the MOSFET. Sorry I was not clear on this point. You are right: allowing current to flow through the harness is a good idea to make the system more immune to noise. I guess the switch in your schematic refers to the fpga output driven in open drain mode. This won't work correctly since gate capacitance would keep the active level indefinitely. In this configuration the fpga output must work in push-pull mode then a standard output, which drives both low and high level. But this would mean twice fpga pins because you need to route input signals elsewhere, and I think you can't afford it. If you want to use the original bidir i/o configuration I suggested, you must change the circuit in one of this ways: - use BJT instead of MOSFETS (the BJT base current will switch off the transistor) - place pull down resistors on MOSFET gates
--- Quote Start --- Simply move to to the receiver end the resistor which pulls up to +12V. Leave on driver end only the MOSFET. Sorry I was not clear on this point. --- Quote End --- Could you please elaborate on this bit? WHere should I move the resistor too on the receiving end?
I can't draw a schematic right now. I'll try to explain with words.Transistor gate/base near FPGA output. Then the harness wire connected to the drain/collector. The other side of the harness wire connects to: 1- the 12V pull up resistor 2- the gate/base of the receiving stage, near fpga input The pull up to 3.3V near fpga input. In other words, both resistors near to the receiver, while transistors are one per side.
--- Quote Start --- How does this look? Is this what you suggested? --- Quote End --- No need for the 5k resistor connected to +12V on the left. The one on the right is enough. Another remark: why do you use an additional +5V supply on the right? Use 3.3V here too. If it's just a matter of MOSFET threshold, select a transistor with lower Vgs. --- Quote Start --- One thing that bothers me is this: I will need the circuit to have 300 IO traces. If I put a transistor on each end and on each trace, I will need 600 transistors per board. Don't you think this is too excessive? --- Quote End --- Those transistors and resistors don't make a great difference: those are small components. Remind you already have to place 300 traces and 300 connectors with wires, which make a more bulky (and costly) hardware.