Output Voltage Higher than Maximum Voltage of GPIO

[Luckyguide]

Dear all,

I have written a code that sends out a PWM signal with a duty cycle of 50% at 12.5 MHz. I am using the DE10-Lite board with the MAX 10 FPGA and Quartus 23.1.1 software on Windows 11. When I uploaded the code and observed the signal through an oscilloscope, I found that the overshoot of the signal reached a maximum value of 4.76V. How would this be possible when I assigned a 3.3V LVTTL pin as the output with a current of 8amps? I tried lowering current to 4 amps, assigning different pin locations, with no success. I also sampled the PWM at a lower frequency of 3KHz, and observed that it still had an overshoot to 4.76V. As well as using a multimeter to detect the output voltage at the GPIO, where I measured a level of approx. 2.5V, which should not be the case as the measured voltage should 50% of 3.3V, e.g. 1.666V.

I have attached the picture of the oscilloscope, where orange is the PWM signal and blue is another PWM signal which is the "NOT" version.

Anybody have any idea what could be the case?

[Mikexx]

I presume the signals are not terminated? I would also keep an open mind over the integrity of measurement in terms of probe and 'scope. Do you have a reference signal on the board to compare with?

Do you really mean either 8 or 4 Amps? How are you measuring this current? Can you elaborate on the context of this current?

Is the Max10 device output limited by protection diodes that don't clam to your 3.3V VCC? In which case 4.7V is quite realistic on account of a reflection. How long is the trace?

Does the Max10 have an internal source resistance capability? Can you load the PWM output at the signal destination?

[Luckyguide]

Thanks for your response,

The signals are not terminated, and I don't have a good reference signal to compare to. I tried making a reference with a lower frequency of 3KHz but that also showed the same problem with voltage overshoot.

The current is what i specified in the pin planner, I didn't measure it during the test.

I'm not quite sure about the protection diodes, as I couldn't find any information about it anywhere. The trace is 10cm if you're referring to the cable length of the GPIO to the oscilloscope probe.

The MAX 10 does not have an internal source resistance capability and I would prefer to not make any circuit changes, as I am wondering why the direct output at the GPIO is not a 50% duty cycle 3.3V PWM signal. Isn't it that this constant overshooting will damage the GPIO of the development board over time if I don't fix the overshoot at the GPIO?

I am aware that I can add capacitors and resistors to stop the overshoot, but I am rather concerned about the behaviour of the development board and I feel like either I have done something wrong in pin planning or I am missing something.

[Mikexx]

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@Luckyguide wrote:

Thanks for your response,

The signals are not terminated, and I don't have a good reference signal to compare to. I tried making a reference with a lower frequency of 3KHz but that also showed the same problem with voltage overshoot.

The current is what i specified in the pin planner, I didn't measure it during the test.

I'm not quite sure about the protection diodes, as I couldn't find any information about it anywhere. The trace is 10cm if you're referring to the cable length of the GPIO to the oscilloscope probe.

The MAX 10 does not have an internal source resistance capability and I would prefer to not make any circuit changes, as I am wondering why the direct output at the GPIO is not a 50% duty cycle 3.3V PWM signal. Isn't it that this constant overshooting will damage the GPIO of the development board over time if I don't fix the overshoot at the GPIO?

I am aware that I can add capacitors and resistors to stop the overshoot, but I am rather concerned about the behaviour of the development board and I feel like either I have done something wrong in pin planning or I am missing something.

---

So the overall device current.

That trace is very long. Simple transmission line theory suggests with an o/c destination the trace will go to 2 x VCC or in your case the voltage is probably limited by protection diodes ~5V. Therefore I might expect to see a nominal 2.5V average.

Can you change the drive current, or the slew rate? I would set these to be the lowest and slowest.

I know you don't want to change the PCB, but you should think transmission line and termination for all signals, especially when driven with sub-ns rise and fall times. 10cm represents a time of ~0.5ns. I hope there is just one destination pin?

A series termination at the source would be best, the alternative is a parallel termination at the destination.

The overriding consideration is does the system work as intended?

[Luckyguide]

I can try to lower the amps, but I can’t change the slew rate.

Yes, there is only 1 destination pin.

The system has not yet been made, i hope to drive a Linear CCD sensor but i’d first like to replicate the signals sent to the CCD by programming it and measuring it using the oscilloscope. I still have to add some other components to complete that. I’ll try to apply your suggestion of a series termination at the source, when I have further info then I’ll post it.

For now I’m trying to fix an issue as my laptop crashed after which somehow doesn’t allow me to upload code to the board anymore. In the meantime, I hope my question can be answered as to how the output voltage can even reach 4.7V if I only send a 1 or a 0 from my program. Theoretically it should then only be 0-3.3V maximum with perhaps a little overshoot?

[Mikexx]

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@Luckyguide wrote:
I can try to lower the amps,

I don't believe the current is particularly relevant.

@Luckyguide wrote:
but I can’t change the slew rate.

Yes, there is only 1 destination pin.

Ok

@Luckyguide wrote:
I hope my question can be answered as to how the output voltage can even reach 4.7V if I only send a 1 or a 0 from my program. Theoretically it should then only be 0-3.3V maximum with perhaps a little overshoot?

---

I have already answered this. If an unterminated transmission line is driven, then the reflected voltage will return and add to the source drive voltage. I recommend you look up about this. An example article:

  https://wiki-power.com/en/%E4%BF%A1%E5%8F%B7%E5%AE%8C%E6%95%B4%E6%80%A7-%E5%A4%B1%E7%9C%9F/#reflection-at-resistive-loads

[FvM]

Hi,
do you know trace transmission line impedance? Depends on width and layer stackup, you can e.g. use popular Saturn PCB toolkit for calculation.
MAX10 LVTTL33 4mA IO standard has about 60 ohm typical output impedance, not far from lower range of expextable trace impedance. In any case you don't get much overshoot at the driving pin but larger overshoot at open trace end. Where do you measure the shown waveform?

I'm not sure if measured 4.7 V is real, it might be also caused by unsuitable probing. It's no easy to measure correct waveforms of fast FPGA output signals with passive probes.

I calculate maximal overshoot magnitude of 4.125 V at open trace end for 60 ohm pin impedance and 100 ohm trace ( 3.3*2*100/(60+100) ), but trace impedance is most likely lower.

[Luckyguide]

I have been able to get my USB-Blaster to work properly again. 

I'd first like to thank you for the responses. The first thing I did was upload the code to the Flash Memory of the DE10-Lite, as I didn't want to keep reuploading my code. I immediately noticed that the output signal was different.

Image 1 represents the PWM of Phi 1 and Phi 2, where the maximum reached a value of 4.76V, this was when I used to upload code to the temporary JTAG.

When I uploaded the same code to the Flash Memory, I saw that the overshoot was a lot less, 4.08V to be exact. Note that this was also without termination and the setup was exactly the same(a female to male pin header was attached to the GPIO and the oscilloscope probe was attached to the male end of the pin). See image 2 for the oscilloscope output of Phi 1.

Lastly I used termination by applying a 220 Ohms series termination between the male end of the pin and the oscilloscope probe. This resulted in image 3, where overshoot was negligible. 

I think that the the resistor compensated for the oscilloscope probe's capacitance, it also better matched impedance(termination), and slowed down signal rising edges. So this would mean that I have to incorporate the resistor into my PCB design right? I just started learning about termination so any advice would be helpful.

[FvM]

Hi,
I believe it's a measurement artifact in the first place, as guessed before. Unfortuantely it's hard to decide about the original waveform without probe connected. If you don't have suitable active probe, I would design termination and determine expectable signal quality based on analysis of PCB impedances.

[Luckyguide]

Thanks for your response, I think my questions have been answered

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