Hi guys,Well I have to communicate two FPGA cyclone V by PCIe, but I dont know if I can use all pins. Here are some doubts about pins - PRSNT#1 :This pin if a hot plugg detec, but If I conected by PCIe two FPGA, How should I use this pin?? - rest : Should I use a pull-up resisten to this pin? - Wake : How should I use this pin? - REFRENTCLOCK: I know that PCIE has clock embbed in his data (encoding 8b/10b makes it possible), so should I use a Clock? - JTAG and SMbus: That are auxiliar signal, How should I use thata pins? Help please, any infomation will be usefull to me Regards
Your question is too wide, it is basically need to know you want to use it as active or passive, then serial or parallel, then is it multi device? End up like combination of active serial active serial multi device or fast passive parallel, or etc.For most combination, nstatus, nconfig, conf_done are to pull up resistor; nCE can be ground or pull down. You can even tie 2 pins together such that they enter user mode together, no delay or leading at timing diagram. It really depend on the configuration you want. Best Regards, Tzi Khang, Lim (This message was posted on behalf of Intel Corporation)
Hi,The PRSNT#1 is the Present# signal for the PCIe. It should be connected to the farthest PRSNT#2 pin/signal depending on the lane width. PERST# Signal The PERST# signal is de-asserted to indicate when the system power sources are within their specified voltage tolerance and are stable. PERST# should be used to initialize the card functions once power sources stabilize. PERST# is asserted when power is switched off and also can be used by the system to force a hardware reset on the card. System may use PERST# to cause a warm reset of the add-in card. PERST# is asserted in advance of the power being switched off in a power-managed state like S3. PERST# is asserted when the power supply is powered down, but without the advanced warning of the transition. The REFCLKp/REFCLKn signals are used to assist the synchronization of the device’s card’s PCI Express interface timing circuits. Availability of the reference clock at the card interface may be gated by the CLKREQ# signal When the reference clock is not available, it will be in the parked state. A parked state is when the clock is not being driven by a clock driver and both REFCLKp and REFCLKn are pulled to ground by the ground termination resistors WAKE# signals should be connected to the other PCIe devices as this is used for link re-activation.