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Matt1
Beginner
408 Views

PCIe Endpoint to PCIe EndPoint communication

Is it possible to communicate between two pcie endpoint Hard IPs in FPGA.

Do somebody tried it?Any references?

the idea is to interface a PCIe device(can be a rootport) to pcie endpoint(in fpga) then the data need to be transmitted to other pcie device from the pcie endpoint(in fpga).So pcie endpoints in FPGA will act as a bridge.

can somebody pls comment on any other mechanism to achieve this?

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5 Replies
JET60200
New Contributor I
114 Views

hi Matt,

I'm also working on a " pcie endpoint" device design in Arria 10, can you point to me some “Gold Reference Design of A10 PCIE Endpoint design ”, which is appreciated very much.

 

Thanks ​

BoonT_Intel
Moderator
114 Views

BoonT_Intel
Moderator
114 Views

Hi Sir,

Yes any EP device can initiate transaction to other EP through a bridge.

But what I am confusing here is you mentioned the FPGA EP will act as a bridge. I don't think we can use the FPGA as a bridge.

So, in your application, you will still need a physical bridge that connecting the 2 EP.

Matt1
Beginner
114 Views

BCT_Intel..thanks for the reply.

its just a misunderstanding about the bridge that i mentioned in my query.sorry for that.

In some intel fpga i found 2 Hard PCie IP.

my question , is it possible to connect these 2 IPs which are configured as ENDPoint, So that one PCie EP receive the data from a RP and other EP will transfer data to another RP.

Do u have some reference designs for this..

you mentioned about bridge is the cutom design(eg: dual port Ram) which need to be interfaced with these 2 Endpoints .Correct me if I am wrong?

BoonT_Intel
Moderator
114 Views

[Matt]is it possible to connect these 2 IPs which are configured as ENDPoint, So that one PCie EP receive the data from a RP and other EP will transfer data to another RP.

[BCT]I believe this is doable, but you need to build a logic within the FPGA to transfer the data data from AVMM/AVST port of one Hard PCIe IP to another PCIe IP. this is a very rare application, I am sorry to said that we do not have this kind of reference design.

One more thing that I curious is if you want to use 2 PCIe IPs from the FPGA connect to one RP. How you going to design the FPGA board's PCIe slot? One PCIe IP connect through slot and another connect through PCIE cable? Please note that A10 PCIE does not support bifurcation, thus you can't have 2 PCIE slot share the same slot.

And yes to your last question. Bridge is use to interface 2 EP.

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