PCIe Gen2 on Cyclone V GT FPGA Dev Kit

[Vijayvithal]

I modified the altera_pcie/altera_pcie_hip_ast_ed/example_design/cv/pcie_de_gen1_x4_ast64.qsys file to support gen2 x4
I generated and compiled the code and tried loading it on the devkit.
While the gen1 sof file enumerates, the gen2 version fails to enumerate.

Both gen1 and gen2 pass verification.
Are there any changes in board settings that are required to get the gen2 bitfile to enumerate?

[Wincent_Altera]

Hi,

1. May I know what is the device OPN that you are using ?
2. Do you capture any .stp ? If not , do appreciate if you can do that, with that we can know where the LTSSM stuck at, hence further debug can be done.
   1. If you not sure how to capture that, please let me know, I can guide you step by step.

Regards,

Wincent_Altera

[Vijayvithal]

What is a device OPN?

I tried installing signaltap and capturing the boot sequence,  but since I need to reboot the machine to get it to enumerate I did not make much progress there.
Please inform about the signals that I need to capture and I will do it.

[Wincent_Altera]

Hi Vijay

What is a device OPN? Is the device ordering number, just want to check if I could replicate this (ONLY IF i have the same device)
Example of device OPN https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/cyclone/v-gt.html

Please inform about the signals that I need to capture and I will do it.

1. npor
2. reset_status
3. nreset_status
4. pin_perstn
5. current_speed
6. dl_ltssm[4:0]

Regards,
Wincent_Altera

[Vijayvithal]

The device is  5CGT–D9-C7N https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/cyclone/v-gt.html
The signals after running  `echo 1 |sudo tee /sys/bus/pci/rescan`

I am connecting to the remote machine via the following steps

```

 ssh -L 1309:localhost:1309 remote

 nohup jtagd

```

on local machine I am running `jtagconfig` to update the connection

After a reboot of remote machine I am not able to trigger a capture because signaltap reports invalid JTAG configuration

[Vijayvithal]

Attaching the project archive file for reference.

[Wincent_Altera]

Hi Vijay,

May I know is this gen2 (fail) design or gen1 ?
What is the version of Quartus you use to compile this design ?

Regards,
Wincent_Altera

[Wincent_Altera]

Hi Vijay,

Any update ? Hope to hear back from you so that we can proceed further.

Regards,

Wincent_Altera

[Wincent_Altera]

Hi Vijay,

I seeing your ltssm is stuck at 00h which is in detect.quiet stage.
This mostly happen due to the host Can't detect far end Receiver.

I suggest to check with the Connectivity problem or Board component problem/

1. Is this plug in to slot that supported gen2 ?
2. do you change the BIOS setting from "auto" to "gen2"
3. Please check your VCCR/VCCT , ensure that it is 1.1v
   

Regards,
Wincent_Altera

[Vijayvithal]

Wincent,
The board is plugged into gen4 pcie slot.

Regarding the pin assignments,

The Board reference manual recommends PCML for the serdes pins.

We are currently using this setting

set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name IO_STANDARD LVDS -to clk_clk
set_instance_assignment -name IO_STANDARD HCSL -to dut_refclk_clk
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to dut_npor_pin_perst
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to dut_hip_serial_rx_in0
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to dut_hip_serial_rx_in1
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to dut_hip_serial_rx_in2
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to dut_hip_serial_rx_in3
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to dut_hip_serial_tx_out0
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to dut_hip_serial_tx_out1
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to dut_hip_serial_tx_out2
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to dut_hip_serial_tx_out3
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

[Wincent_Altera]

Hi VIjay,

I seeing your question is addressing in another platform

Is there anything else you think I could help you in this forum thread ?

Regards,

Wincent_Altera

[Vijayvithal]

We are getting a faster rate of response on IPS and are making progress there.
This thread can be closed.

[Wincent_Altera]

Hi Vijay,

Thanks for your response, please be understand that we are in full commitment to support any of our customer either it is in forum or IPS. Please accept my sincerely apology for some unexpected delay causing in this thread.

I am glad that your issue making progress in our IPS platform. If there is any new issue come in , you may file a new forum thread/ips. We will be there to support you. Thanks for reaching to us anyway.

Have a nice day.

Regards,
Wincent_Altera