PCIe Hard IP Status signals and msgdma

[Altera_Forum]

Hi, I'm doing PCIe Hard IP with msgdma.--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------In the Cyclone V Avalon-MM Interface for PCIe Solutions user guide document, Hard IP Status signals as follows: -------------------------------------------------------------------------------------------------------------------------- dlup_exit -- This signal is asserted low for one pld_clk cycle when the IP core exits the DLCMSM DL_Up state, indicating that the Data Link Layer has lost communication with the other end of the PCIe link and left the Up state. When this pulse is asserted, the Application Layer should generate an internal reset signal that is asserted for at least 32 cycles. ----------------------------------------------------------------------------------------------------------------------- hotrst_exit -- Hot reset exit. This signal is asserted for 1 clock cycle when the LTSSM exits the hot reset state. This signal should cause the Application Layer to be reset. This signal is active low. When this pulse is asserted, the Application Layer should generate an internal reset signal that is asserted for at least 32 cycles. ----------------------------------------------------------------------------------------------------------------------------------- My question : 1. Does the generated reset signal to reset the the Application Layer ? But how the PCIe Hard IP reset? ---------------------------------------------------------------------------------------------------------------------------------------- 2. HOST -- PCIe -- msgDMA -- Application Layer -- SRAM. PCIe may die after several days , it's the DMA can't read enough data , so the DMA wait for it , so die . How to solve it ?