Community
cancel
Showing results for 
Search instead for 
Did you mean: 
Altera_Forum
Honored Contributor I
817 Views

PCIe Hard IP build error

i add two PCIe hard IP in my project(the FPGA device support two PCIe core),but Quartus show the error as follow, i am new to FPGA,could anybody help me solve the problem ? thanks very much! 

 

------------------------------------------------------------------------------------------------------------------------------------ 

 

Error (14566): Could not place 2 periphery component(s) due to conflicts with existing constraints (1 Hard IP(s), 1 Receiver channel(s)) 

Error (175020): Illegal constraint of Receiver channel that is part of Avalon-MM Cyclone V Hard IP for PCI Express altpcie_cv_hip_avmm_hwtcl to the region (0, 36) to (0, 38): no valid locations in region 

Info (14596): Information about the failing component: 

Info (175028): The Receiver channel name: pcie1_rx_p 

Info (175015): The I/O pad pcie1_rx_p is constrained to the location PIN_R2 due to: User Location Constraints (PIN_R2) 

Info (14709): The constrained I/O pad is contained within a pin, which is contained within this Receiver channel
0 Kudos
5 Replies
Altera_Forum
Honored Contributor I
39 Views

We don't have crystal balls. 

 

What device are you using? What settings are you using for your hard-ip core? What pins are you constraining the transceivers and clocks to?
Altera_Forum
Honored Contributor I
39 Views

the device is Cycone V 5cGXFC7D6F31C7ES,my project use two Avalon-MM Cyclone V hard IP for PCI-e,and all devices are native endpoint X1,the pin pcie1_rx_p is the RX channel in PCIe,i set it to PIN_R2 (GXB_L2) .

Altera_Forum
Honored Contributor I
39 Views

And what about all the other pins? If you have two Hard-IP cores, you will have at least 4 transceiver assignments, plus clock pin assignments, etc.

Altera_Forum
Honored Contributor I
39 Views

Section 1-5, P319 of the cyclone v handbook (https://www.altera.com/en_us/pdfs/literature/hb/cyclone-v/cyclone5_handbook.pdf). 

 

 

--- Quote Start ---  

 

The PCIe Hard IP blocks are located across Ch 1 and Ch 2 of bank GXB_L0, and Ch 1 and Ch 2 of bank GXB_L2. 

 

--- Quote End ---  

 

 

According to P31 of the cyclone v pin information (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/dp/cyclone-v/5cgxfc7.pdf), Pin R2 of the F31 package corresponds to channel 0 of GXB_L2 and is therefore not supported. Pins N2 and K3 are supported as they correspond to channels 1 and 2.
Altera_Forum
Honored Contributor I
39 Views

thanks for your help,i solve the problem now,it's all because of the "pin_perst" pin ,each Hard IP core should have a single "pin_perst" ,but in my original project,the two PCIe core share a pin_perst signal ,that's the problem.