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In our system FPGA 5CGXFC7D6F27I7N and CPU TMS320x are connected via PCIe x2 GEN1. During link training LTSSM goes through such states:
- 0 Detect.Quiet
- 1 Detect.Active
- 2 Poling.Active
- 3 Polling.Compliance
- 2 Polling.Active
- 4 Polling.Configuration
- 6 config.Linkwidthstart
- 7 Config.Linkaccept
- 9 Config.Lanenumwait
- 8 Config.Lanenumaccept
- A Config.Complete
- B Config.Idle
- F L0
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