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PCIe avalon-mm Slave on cyclone 10gx development kit.

Kalpitha
Beginner
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Hello!

I started to work with the Cyclone 10gx development kit recently. I am interested in PCIe Hard IP . I have downloaded the example designs and I have compiled them and tested on a PC, which works fine.
I want to write my own Avalon_mm slave, where I do a simple decoding of address to blink the LED's on development kit board. Well my main task is to control some registers in the FPGA through PCIe interface, the read and write of few registers mostly, for the moment not any complicated image data streaming and all.

For this, I have instantiated PCIe hard IP , and configured the application interface to be Avalon_mm, brought out the avalon_mm slave bus to external. And I have connected my led_blinking slave to PCI hard IP core.

This code compiles without any errors.

I use 'RW Everything'  tool on the PC to detect the PCIe and to dump memory.
My compiled design is tested with this tool. here I see the PCIe hard IP is detected my PC. But the 'BAR' is not assigned. BAR0 and BAR2 are enabled during configuration. But this is not detected. therefore I cannot read or write to and address.

When I look into the example design. in the hierarchy, I see mm_interconnect_0 component which is missing in my design.
Can you please help me figure out what other interface signals I have to connect to get mm_interconnect_0 component on my design?

If I connect an onchip memory IP as a slave instead of my slave. I see this mm_interconnect_0 in the hierarcy.

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ZH_Intel
Employee
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Hi Kalpitha,

 

Thank you for reaching out.

Just to let you know that Intel has received your support request and currently we are confirming the details with our internal team.

I shall come back to you with findings.

 

Thank you for your patience.

 

Best Regards,

ZulsyafiqH_Intel


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Kalpitha
Beginner
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Hello ZulsyafiqH_Intel,


Thank you for responding. I want to add few more findings I did during these days.

I have an update on this issue.

I found out that it is better to create my user code as a new IP (Avalon Slave), add my IP to the platform designer and connect the Avalon master of Hard PCIe IP to the my slave.


I have attached the screenshots of the platform designer and I have uploaded my new updated VHDL code of the Avalon slave.

 

On the PC (computer #1,where the Cyclone 10gx development board is on PCI slot) I use the tool "RW Everything", to detect the PCIe and to read and write to the memory.

With the project that I have created," RW Everything" detects the PCI Hard IP I have instantiated in my project. But unfortunately, read or write is not triggering at address "800000000"(It is the start Base address of my slave)

In the Platform designer where I have connect my Slave, the address allocated is quite huge and I am unable to change the end address, Memory start and end is the problem or the User Slave I have written is not a right way of defining the Slave?

 

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Kalpitha
Beginner
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Hello Team,

 

I have some more updates on my project.

I have modified PCIe hard IP as a 32 bit Avalon-mm aplication layer.

I have also modified my custom  Avalon-mm slave accordingly.

I resolved the isuue  with the address. I have connected two slaves for the PCIe hardIP.

Currently I have no errors, But I am unable to perform any read or write to the BAR assigned by the host PC.

 

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ZH_Intel
Employee
917 Views

Hi Kalpitha,

 

Apologize for the delayed response as we encounter some technical difficulty.

I'm glad you are able to resolve the address issue.

For the unable to perform any read or write to the BAR, we suggest you to please check lspci log and check if Memory and BusMaster bit value. These bits have to be enabled, then only host can access BAR.


Thank you.

Best Regards,

ZulsyafiqH_Intel


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ZH_Intel
Employee
892 Views

Hi Kalpitha,

 

Good day.

I wish to follow up with you about this case.

Do you still have further inquiry on this case?

If there is no further inquiries, I will transition this thread to community support. 


Thank you.

Best Regards,

ZH_Intel


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ZH_Intel
Employee
838 Views

Hi Kalpitha,

 

We do not receive any response from you to the previous reply that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread.


Thank you.

Best Regards,

ZH_Intel


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