Quartus 19.3 / Intel provides a sample design pcie_ed with a pcie IP connecting to a simple RAM. It runs properly on the Development Kit for Cyclone 10 with a 2 lane gen 2 configuration, 64 bit @ 125MHz.
I have a design based on 10CX105YU484. This board gets properly enumerated using the same design. The provided device driver (altera_pice_win_driver / Altera PCI API Driver) is loaded on my Windows 10 x64, no issue is shown. Running the Interop_software Alt_Test.exe on this board failes. Using my own driver which works with the Dev Kit, shows that only 0xffffffff can be read back. Since the board is enumerated I assume the PCIe IP is partially working. Routing out the Avalon chipselect and write signals to test points do not show any activity. While on the Dev Kit I can properly measure these control signals.
The entire design relies on IPs from Intel, I wonder what I am missing. Any suggestion were to go from here would be very much appreciated.
