PCIe gen 4 - 16 lanes in Agilex: maximum rate

[Avi_V_888]

Hi'

I using PCIe gen 4 (16 lanes) (512bit/500MHz clk , payload size:256B) CORE, in Agilex device: AGFB014R24A2E2VR0.

The theoretical rate is: 32GB/sec  (of course it is not possible to reach such a rate in reality)

The maximum rate at which I was able to transfer information using DMA is 27.5GB/sec (This is not a limitation of the computer itself).

Is it possible to reach a higher rate?
And if so, what could be the reason I'm not succeeding? (Maybe same configuration in the core)

Thanks

Avi

[Harris]

Hi Avi,

1, Do you use your own DMA design?

2, What is the MPS and MRRS setting?

BR/Harris

[Avi_V_888]

Hi Harris

First of all thank you.

Yes I am using my own DMA, but I see that what prevents me from sending data from the DMA to the PCIe Core is that the Core "ready" signal is drops to zero.

The MPS (maximum payload size)  is: 256 Byte

I do writeד from the Core to the PC and not readings, means that MRRS is not relevant to me

[Harris]

Hi Avi,

1, Because there are lot of factors impacting throughput, including 128b/130b encoding in physical layer, acknowledge and flow control update in DLL, packet overhead, payload size, DMA design, etc, the throughput can't get to the theoretical data rate(32GB/s).

2, I suggest you try MPS 512B. From factory test result, the writing throughput(without reading) can get more than 29GB/s with MPS 512B.

Thanks

Harris      

[Avi_V_888]

Hi Harris,

In my application, the MPS is 256B.

I just want to know the maximum rate that can be achieved for 256B (Just as you mentioned that the maximum rate for 512 is 29GB)

Thanks

Avi

[Harris]

Hi Avi,

Your writing data rate(27.5GB/s) with MPS 256B is very similar with the test result from factory.  Thanks.

BR/Harris

[Avi_V_888]

Thank you !!!