PCIe gen 4-6 lanes Agilex: maximum number of clks ready signal disabled

[Avi_V_888]

Hi,

I using PCIe gen 4 (16 lanes) (512bit/500MHz clk , payload size:256B) CORE, in Agilex device: AGFB014R24A2E2VR0.

Tests performed found that the maximum number of clks that "ready" signal was disabled is: ~32,000, Which requires me to place a very large FIFO/ using DDR and consume a very large bandwidth to absorb the data that comes to the core. (because the data arrives at a near but lower rate than the PCIe and without back pressure - so that it is only necessary to deal with the momentary unavailability of the core).

Is it possible to somehow configure the core so that its unavailability is distributed over time and does not arrive in such a long sequence? @Harris 

Thanks

Avi

[Harris]

Hi Avi,

Yes. It is possible that you can use TX flow control interface to allocate the transmission in advance, instead of depending on 'ready' fully in your situation. For TX flow control interface, please refer to user guide. Thanks.

BR/Harris

[Avi_V_888]

Hi Harris,

The source that feeds the PCIe core in data (and from there the core transfers it to the PC) works in real time mode.
Therefore TX flow control interface will not help here.
The problem will be solved if it will be possible to configure the core so that the ready signal will not be '0' for such a long time continuously.

Avi

[Harris]

Hi Avi,

Unfortunately, there is no configuration for the core for this behavior. Thanks.

BR/Harris 

[Avi_V_888]

Ok

Thanks