Hi, i'm using Stratix 10 AFU with HSSI configured in a serial loopback. According to the documentation, the PHY IP is configured as PCS Direct with 32 bit PMA width, and bit 79 is the rx_data_valid.
However, i'm observing that before the serial loopback is asserted, bit 79 become high and kept high even after the serial loopback is asserted.
Is this an expected behavior when using serial loopback? Because i'm using that signal to write the data into a FIFO, and this behavior flooded the FIFO with wrong data.
As I understand it, you have inquiries related to the rx_data_valid for the S10 XCVR. To ensure we are on the same page, just woud like to check with you on the following:
1. What is the specific XCVR PHY that you are using? Is it L/H-Tile Native PHY?
2. What is the specific Quartus version that you are using? Just wonder if you have had a chance to try with different Quartus version to help isolating Quartus version dependent problem?
3. Just wonder if you have had a chance to perform a functional simulation ie in Modelsim to check on the behavior?
4. Before the serial loopback is asserted, what is the lock status of the CDR?
5. If you are using external loopback (no serial loopback used), ie plug and unplug cable, is there any difference in the observation?
Please let me know if there is any concern. Thank you.
1. Referring to this documentation (https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-opae-nwi-d5005.pdf), yes i'm using L/H-Tile Native PHY, although i can't access the IP directly in Quartus.
2. I'm using quartus version 19.2.0 Build 57 Pro Edition. This is the default quartus version when configuring the tools to use with Stratix 10 PAC.
3. Apparently with AFU the simulation is done via ASE, but when using HSSI, ASE is not available. So I haven't been able to check from the simulation. Is there any other way for me to try this?
4. serial loopback is asserted when lockedtodata and lockedtoref are both 0. It happened after analogreset falling edge and digitalreset_stat rising edge. After a while the rx_data_valid is asserted when both analogreset and digital reset are 0, but digitalreset_stat is 1 (deasserted after several cycle).
5. I can't checked this yet for now, because i'm using the FPGA on intel Devcloud.
Also, I found another problem. The digitalreset seems to be triggered repeatedly after the first reset, is there any guideline to troubleshoot the rst_controller?