PLL Critical Warning when generating less than the Max frequency

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

PLL Critical Warning when generating less than the Max frequency

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hi ,

am using simple PLL instantiated with input of 50MHz and generated a 5KHz, but am getting this below critical warning

"Critical Warning (176584): Output pin "pll_5KHz" (external output clock of PLL "pll:pll_inst|altpll:altpll_component|pll_altpll:auto_generated|pll1") uses I/O standard 2.5 V, has current strength 16mA, output load 0pF, and output clock frequency of -0 MHz, but target device can support only maximum output clock frequency of 238 MHz for this combination of I/O standard, current strength and load"

am generating 5Khz which is less than a 238MHz max then also why am getting this critical warning......

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