PLL Dynamic Reconfiguration for Stratix III

[Altera_Forum]

Hi everyone, 

 I have a scenario where I need to reconfigure a PLL to handle a wide variation in input frequency (100MHz - 250MHz). After doing a little research, the simplest solution seems to be dynamic PLL reconfiguration, using 2 Megawizard-generated designs. After looking into the IP options available, I decided to generate a simple state machine to load the 2 serial streams and trigger the reconfig. I used signalprobe to bring out my control signals so that I could comapre them to a simulation using Altera's reconfig device and the 2 serial streams are identical. In the lab, however, no matter which of my 2 streams I load, the clock outputs are junk (even though the PLL asserts the lock signal), and DO NOT CHANGE when I change the serial stream. I tried a number of test streams, none of them had any effect.   I am using a Left/Right PLL which reportedly uses a 180-bit serial data stream.   Has anyone successfully implemented PLL reconfiguration in a Stratix III? Has anyone done it with a custom implementation (i.e. without using Altera's PLL_RECONFIG block)?   Thanks!

[Altera_Forum]

Hello, 

I managed to implement it and used ALTPLL_RECONFIG; my target device was a Stratix III but I had a different frequency range (40MHz -> 65 MHz). I followed AN 454 as example but developed my own state machine to give a reset to the PLL after it locked. I also used some logic to test the frequency (that board had another clock that was considered "safe" and was used for some built-in tests) and, if necessary, retrigger the reconfiguration.   I did it with Quartus II 9.0 and I had problems with the simulation: the result was not identical to physical device (service request suggestion was to use the Advanced Parameters Configuration).