PLL: Fvco and Fout

[Altera_Forum]

i am confused with the fvco and fout. Is there anyone to clarify it? 

 FYI, i refer to cyclone III PLL. fvco: Min 600M and Max 1300MHz fout: Max 450MHz  In the megawizard, i can set the output frequency to 1300MHz and below the 600M. can anyone elaborate on it?  Besides, in the PLL architecture, the multiplier in the divide form? Is it mean that the multiplier is < 0 for multiplication purpose?

[Altera_Forum]

--- Quote Start ---  In the megawizard, i can set the output frequency to 1300MHz.  --- Quote End ---   May be you can. But it's meaningless, because no FPGA logic element can operate at this frequency. Surely the design won't compile.  Your apparently refering to Cyclone III. In my opinion, the PLL description in the Altera hardware manual is very clear. The VCO frequency range is simply restricted by the oscillator hardware. Also PLL output frequency and phase-frequency detectector (PFD) have frequency restrictions. These properties restrict already the usable range for N,M and C frequency dividers. Furthermore, they have to be positive integers > 0. You shouldn't confuse the actual N,M and C value with the frequency ratio displayed by the MegaWizard. But you'll recognize, that the MegaWizard does only accept frequencies, that can be represented by integer N,M and C factors.  P.S.: M is usually designated multiplier, because it causes the VCO to operate at M*fPFDin.