PLL Phase-locked loop clock detection

[TabetS]

Agelix 7 series chip hard ip is used to complete the project. Now the incoming clock is used as the special clock for transceiver, and the outgoing clock through syspll is also a special clock. Now when the clock is faulty, is there any special way to check whether the input and output clocks of the PLL are normal

[lixy]

Hi there,

If you want to check if the internal signal is normal, did you try using SignalTap to capture the waveform?

Thanks & Regards,

Xiaoyan

[lixy]

Hi there,

Not sure if you have any further questions?

1, "Now the incoming clock is used as the special clock for transceiver, and the outgoing clock through syspll is also a special clock. " Can you help explain what the incoming and outgoing block refers to? For example, is it the input/output for PLL, certain hard IP or FPGA?

2, "Is there any special way to check whether the input and output clocks of the PLL are normal?"

Do you mean only during debugging? Or you meant you want a module to detect and report error within the FPGA project?

Best Regards,

Xiaoyan