PLL Reconfig counter_param question

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

PLL Reconfig counter_param question

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hi, i am trying to reconfigure my pll and i ran into a problem and cant find answers for it. i am hoping you guys can help me out here.

while trying to reconfigure a pll that has two outputs, c0 and c1, i selected counter_type to be C0, then for counter_param[2..0] i dont understand what option to select, high count? low count? bypass? And finally what value to pass in the data[9..0]?

regards,

pratish

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