PLL Tuning

[Altera_Forum]

Hello. 

 I am slightly confused about tuning a PLL output for an SDRAM clock and wondered if someone here could answer a couple of questions.   Following this example [http://www.altera.co.kr/_altera/html/_excalibur/nios-sdram-tuning/sdram_pll_tuning.pdf] I am getting confused about some of the language.   The PDF states:    SDRAM Clock Can Lead System Clock by: Minimum of:  tcoutmin(FPGA)–th(SDRAM) = 2 ns –1 ns = 1 ns  tclk–thz(SDRAM)–tsu(FPGA) = 10 ns –5.5 ns –2.4 ns = 2.1 ns   (And a similar set for Lag)   What are the system clock and SDRAM clock? I take it one of them is the actual output with the phase shift? (SDRAM clock im thinking this one is) What about System Clock, does this refer to the actual data, i.e. the 'clock' that would clock it correctly if it existed?     The SDRAM core documentation says that I should read the appropriate delay values for the FPGA from the timing analysis done on compilation, but I can't find any values in either the Classic Timing Analyzer or TimeQuest reports that the examples mention. Do I have to set it to analyze the pins relating to the memory in this way specifically? 

[Altera_Forum]

Hi sebastian, 

- system clock is the clock which feeds to your internal fpga devices, i.e. Nios processor or other devices configured in fpga - sdram clock is the clock signal which goes outside and drives the clk pin on the sdram  Usually there is a relevant delay between sdram clock source (the pll which also generates system clock) and the sdram pin, whereas system clock has well controlled delays, being wholly inside the fpga. For optimal performance you should account for this delay, normally applying a phase lead to sdram clock.  For example, on my board I have both clocks at 100MHz, with sdram clock leading sys clk by 27 degrees. Results from timing analyzer help you to find out the optimal phase shift, depending from fclk and setup/hold requirements of your devices.

[Altera_Forum]

Hi Cris72. 

 Thanks, those equations are making more sense now.   So essentially what those equations are working out is the maximum amount of time the SDRAM clock can rise before the system clock (which all the SDRAM data are synchronized to), the first equation being for write and the second for read. So you take the minimum of these so no matter whether reading or writing its never too far out. Is that correct?   Then you calculate a similar value for the lag, and that provides the window around the system clock edge that the SDRAM clock can operate in, and you adjust the phase so that it sits in the centre of this, right?     As for the timing analysis (using Classic), I can see the reports for tsu, tco and th for the FPGA, but I had a couple of questions about using them: 1. I take it I should take the worst case values for the pins relating to the memory rather than the worst case for the entire design right? 2. In the lead/lag equations they use the maximum and minimum clock to output delay (tcout) of the FPGA, but my timing analysis report only has one set, which I am assuming are the maximum. Am I missing something or do we just use these?   Thanks again.

[Altera_Forum]

Hi. 

 OK ive done the PLL tuning and my memory is working very well, thanks again!   I was wondering if someone could check something for me however.   As it is now, I can take the memory up to 90Mhz and it passes the simple tests fine, but if I take it to 100 it starts to fail.   The reason I suspect it might be my calculations for the PLL tuning as opposed to simply limitations of my board is because 90Mhz is the frequency at which the Tclk period becomes small enough that the Lead & Lag times of the read operations become smaller than those of the write operations. The phase shift calculated at 90Mhz is almost identical for that calculated for all frequencies below it, but any higher and it deviates more and I begin to encounter errors.   My SDRAM has the following parameters: Tac/hz = 5.4 Toh = 2.7 Tsu = 1.5 Th = 0.8   The timing analysis reports for my FPGA: Tsu (smallest for SDRAM pins) = -0.493 Tco (highest for SDRAM pins) = 7.008 Th (highest for SDRAM pins) = 0.679   I have calculated my phase shift as +1.8005ns at 100Mhz SDRAM clock.   Does this look right?

[Altera_Forum]

HI. 

I need the phase shift for Cyclone II EP2C35 Board.  50 MHz -3ns pll won't work.