The following system is available:
- PLL - 1 ref_clk, 2 clk_out (1x and 10x ref_clk)
- FSM which searches for a sequence in the input, if it does not find it, performs a phase shift of one of the output frequencies (bit-slip (1x) and "center-aligned" (10x))
The problem is that you can see how the 10x shift is performed, but the 1x shift does not occur.
c0 - 1x ref_clk
c1 - 10x ref_clk
The signals, as can be seen from the figure, are set correctly (according to pdf)
So what prevents us from working so we want to?