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PLL phase shift does not work

EBoln
New Contributor I
483 Views

The following system is available:

- PLL - 1 ref_clk, 2 clk_out (1x and 10x ref_clk)

- FSM which searches for a sequence in the input, if it does not find it, performs a phase shift of one of the output frequencies (bit-slip (1x) and "center-aligned" (10x))

 

The problem is that you can see how the 10x shift is performed, but the 1x shift does not occur.

c0 - 1x ref_clk

c1 - 10x ref_clk

 

shift.pngThe signals, as can be seen from the figure, are set correctly (according to pdf)

 

So what prevents us from working so we want to?

 

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5 Replies
SreekumarR_G_Intel
217 Views

Hello,

Can you share the design files to check further ?

 

Thank you ,

 

Regards,

Sree

EBoln
New Contributor I
217 Views

which part? I can send FSM, which performs a phase shift

SreekumarR_G_Intel
217 Views

can you send me the .qar file (archive file for all the files ) which help me to understand ?

SreekumarR_G_Intel
217 Views

Can I close the case or kindly let me know how i can help you further ?

 

Thank you ,

 

Regards,

Sree

EBoln
New Contributor I
217 Views
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