Partial Product Multiplier example

[Altera_Forum]

The partial_product_mult.v circuit allows users to efficiently pack multiplication logic into Altera’s FPGA devices when it is necessary to do so. The circuit features independent parameterized input widths, programmable pipeline stages and the selection between signed and unsigned multiplication. The programmable pipeline stage option allows you to find the most optimal setting between area and speed.  

 Included with this example is the partial_product_mult.v encrypted design file, two example design files and one simulation file. The partial_product_mult.v file is an encrypted Verilog file which can be added to the file list of any Quartus II project which uses the partial_product_mult module. Any valid Quartus II license will be able to decrypt the file during synthesis.  The two example files (ppm_example.v and ppm_example.vhdl) show how one can instantiate the core in these languages. Either of these designs can be used as a quick demonstration of the circuit and its capabilities.

[Altera_Forum]

Thats Great!

[Altera_Forum]

thanks very much！！顶

[Altera_Forum]

I am implementing a floating-point matrix multiplier. In the Floating-Point Megafunctions user guide, there is one example of 2x8 matrix multiplier. Two example files are: 

■ altfp_matrix_mult_designexample.zip (Quartus II design files) ■ altfp_matrix_mult_ex_msim.zip (ModelSim®-Altera files) But, the links are dead. Do you know where I can find these example files?   Thanks.     Lily 

[Altera_Forum]

See the following post: 

http://www.alteraforum.com/forum/showthread.php?t=6743&referrerid=2226  Please try not to double post.  Jake

[Altera_Forum]

--- Quote Start ---  The partial_product_mult.v circuit allows users to efficiently pack multiplication logic into Altera’s FPGA devices when it is necessary to do so. The circuit features independent parameterized input widths, programmable pipeline stages and the selection between signed and unsigned multiplication. The programmable pipeline stage option allows you to find the most optimal setting between area and speed.   Included with this example is the partial_product_mult.v encrypted design file, two example design files and one simulation file. The partial_product_mult.v file is an encrypted Verilog file which can be added to the file list of any Quartus II project which uses the partial_product_mult module. Any valid Quartus II license will be able to decrypt the file during synthesis.  The two example files (ppm_example.v and ppm_example.vhdl) show how one can instantiate the core in these languages. Either of these designs can be used as a quick demonstration of the circuit and its capabilities.  --- Quote End ---   thank u for the code