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Pcie link training failed (CycloneIVGX)

Altera_Forum
Honored Contributor II
‎09-25-2016 03:20 PM
1,121 Views

Hi all! 

 

I have problem with link training between FPGA(CYIVGX) and DSP. 

 

DSP: Ltssm alredy located at state 0x00 and 0x01 (detect.quiet and detect.active). 

FPGA: Ltssm alredy located at state 0x03 (polling.compliance). 

 

I do not understand what is the reason of my problem. 

 

I'm used megafunction IP Compiler for PCIe (without QSYS) and ALTGX_RECONFIG. 

 

http://www.alteraforum.com/forum/attachment.php?attachmentid=12739&stc=1 http://www.alteraforum.com/forum/attachment.php?attachmentid=12740&stc=1 http://www.alteraforum.com/forum/attachment.php?attachmentid=12741&stc=1
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Altera_Forum
Honored Contributor II
‎03-30-2018 01:42 PM
329 Views

Hi, Did You solve this problem? 

I have a similar problem. 

I have TMS320C6655 and 5CGXFC7D6 connected on my board. In most power-on link training is correct. But sometimes LTSSM in FPGA hang in Polling.Compliance.  

Why Polling.Compliance arise? It seems to don`t arise in normal operation. Can I prevents the LTSSM from entering Compliance?
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