Performing user access to the configuration serial flash device

[EugenyB]

Cyclone III. I need access to the serial flash device (W25Q128) after configuration completes.

I am unable to select pins connected to the flash chip using my "user" code. Whatever I set in the device properties for the programming pins I get error from Quartus (maybe I do something wrong).

I tried to use "cycloneii_asmiblock" module (the way asmi module is using it), but for some reason user mode does not start at all, I suspect FPGA does not finish proper configuration because I use this module improperly.

What is the correct way to access serial flash chip - used for FPGA configuration - in user mode?

Is there any documentation?

[Ash_R_Intel]

Hi Eugeny,

The user guide, Generic Serial Flash Interface Intel® FPGA IP User Guide may help you. Below is the link:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-gen-sfi.pdf

Let us know if this helps.

Regards

[EugenyB]

Hello, thank you very much for the document.

Magically the "cycloneii_asmiblock" started functioning properly, and I was able to access (read) flash with up to 45 MHz clock speed. Unfortunately it is not enough and I need it at 75 MHz, but was unable to achieve this speed - either because of board layout, 10 pF caps/BAT54s on the lines (per datasheet recommendation) or just because pins do not support this speed.

Considered using W25Q128FV with "Fast read dual I/O" command, but it appeared that in AS configuration mode the data pins are only in one mode input or output, and it not possible to switch ASDO pin to input mode. Can not get why is this because FPGA must not need configuration device after configuration is finished (because of partial reconfiguration capability?).

[Ash_R_Intel]

Hi Eugeny,

The ASDO pin is a dedicated output pin in Active Serial (AS) mode. It can be an input during configuration while in Passive Serial (PS) and Fast Passive Parallel (FPP) modes. 

It can be used as user I/O after configuration.

Refer below Pin Connection Guidelines:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/dp/cyclone3/pcg-01003.pdf

Regards.

[Ash_R_Intel]

Hi Eugeny,

The ASDO pin is a dedicated output pin in Active Serial (AS) mode. It can be an input during configuration while in Passive Serial (PS) and Fast Passive Parallel (FPP) modes. 

It can be used as user I/O after configuration.

Refer below Pin Connection Guidelines:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/dp/cyclone3/pcg-01003.pdf

Regards.

[EugenyB]

>It can be used as user I/O after configuration.

Do I understand it properly - if I use AS configuration mode, the ASDO pin will only be an output in user mode? Or can I configure it do be bi-directional?

[EugenyB]

Some progress here. I was able to allocate 4 serial flash pins in the design, and project compiled without problems, declaring DI/DO as input/output pins. So now testing stage.

I was doing the stupid mistake - trying to allocate these 4 pins of serial flash without removing cycloneii_asmiblock from the design, and this cycloneii_asmiblock was hijacking programming pins before high level module and of course the module was failing to see these pins as available for the design.

[Ash_R_Intel]

Hi Eugeny,

Glad that you could make some progress.

To your earlier question,

>It can be used as user I/O after configuration.

Do I understand it properly - if I use AS configuration mode, the ASDO pin will only be an output in user mode? Or can I configure it do be bi-directional?

ASDO pin can be used as a normal I/O once configuration is over. During config in AS mode, it is by default an output only.

Let us know if the case can be closed. You may reopen it in case you still face the issue.

Regards.

[EugenyB]

It worked in general, but I still have intermittent problems. Working at 37.6 MHz, some builds do not read data bits properly. Not completely (so that I can recognize data by the eye), but some bits are invalid. I have tried Quartus options for the pins:

// serial flash chip interface

(* altera_attribute = "-name FAST_OUTPUT_REGISTER ON" *)

output wire SF_DCLK,

(* altera_attribute = "-name FAST_OUTPUT_REGISTER ON" *)

output wire SF_NCS,

(* altera_attribute = "-name FAST_OUTPUT_REGISTER ON; -name FAST_INPUT_REGISTER ON" *)

inout wire SF_IO0,

(* chip_pin = "13", altera_attribute = "-name FAST_OUTPUT_REGISTER ON; -name FAST_INPUT_REGISTER ON; -name io_maximum_toggle_rate 0" *)

inout wire SF_IO1

it helps somehow, but not always. I can not release unreliable project, and can not lower the operating frequency. I will have to drop using this chip for this project if will not find suitable solution or mitigate the problem.

Unfortunately there're ignored assignments in the Fitter section:

Fast Input Register -- SF_IO0 -- ON -- Compiler or HDL Assignment

Fast Input Register -- SF_IO1 -- ON -- Compiler or HDL Assignment

however I feed registers with this bidir input:

r_serial_flash_output_data[31:0] <= { r_serial_flash_output_data[29:0], SF_IO1, SF_IO0 };

As I understand with the current setup Quartus fits output register to the nearby cell, but input register may appear at distance causing timing problem.

What can I do not force Quartus putting input registers into the cell nearby to the pin? What is wrong in my setup forcing Quartus ignoring fast input register assignment?

Please help me.

[EugenyB]

I have solved the problem. The W25Q128 is properly working at 56 MHz, even with additional load attached (scope / download cable).

Thank you for your support.

[Ash_R_Intel]

Hi,

Good to know that the issues are solved. Closing the ticket.

Thanks.