We are trying to migrate our Design from Max II to Max V CPLD in our application.
1) Could you explain how the existing source code has to be used completely ? What are the things to be considered while doing this Design change ?
2) Can the Digital Output pin be used for generating a clock of 14.745 MHz for Microcontroller?
3) Link for Example codes for Interfaces like UART,SPI. What is the maximum frequency at which SPI can be generated ?
1) For source code migration, you need to re-synthesize the design in Quartus version supporting MAX V. https://www.intel.in/content/www/in/en/programmable/downloads/download-center.html#
2) Refer following link for the maximum frequency that can be achieved based on your device and IO standard selection: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-v/max5_handbook.pdf#page=74
Your requirement of 14 MHz can be met.
3) There are several design application notes available. Refer https://www.intel.in/content/www/in/en/programmable/products/cpld/max-series/max-v/support.html.
Once you create a new project and select a MAX V device, supported IPs can be also be found in Quartus IP catalog.
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