Platform Designer bug: AXI4-Lite Slave interconnection to AXI4 Master

[adrianf0]

According to the Platform designer documentation, the AMBA 4 AXI-Lite slave can be interconnected to AXI4 master. However, in such a case, rlast signal is not generated. The problem seems to be related to altera_merlin_bust_uncompressor module which seems to have issue with Burst=1 (AXI-Lite). One can see in the enclosed waveform from SignalTap, that source_endofpacket strobe is never generated as assignment:

assign source_endofpacket = sink_endofpacket & last_packet_beat;

is never true in the waveform.

[GuaBin_N_Intel]

Are you using burst or single transfer ?There is some requirement when using AMBA4 AXI-Lite slave https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qps-platform-designer.pdf, 3.13.5.1.

[adrianf0]

Hi @GNg​ , no I don't use bust transfer: according to AXI4-Lite spec all transactions are burst length of 1.