Possible Compatibility Issue Between Intel Cyclone 10 GX Dev Kit and Xilinx FMC-105-Debug

[Alex02]

I am working with the Cyclone 10 GX Dev Kit and have successfully run programs on it before.

I am trying to use the Xilinx FMC to debug signals from the FPGA and eventually communicate with another device. 

Whenever I have the FMC plugged in to the Cyclone 10 GX, the JTAG chain is broken. It throws an error saying it can only see the USB blaster and not the FPGA device. When I remove the FMC, everything works fine. 

Is there a hardware compatibility issue here? 

If yes, what mezzanine cards would work with the Cyclone 10 GX?

Xilinx FMC 105 Debug 

Intel Cyclone 10 GX Dev Kit User Guide 

[ak6dn]

What makes you think the AMD/Xilinx FMC105 card is in any way pinout compatible with the Intel/Altera Cyclone 10 GX board?

They may both use the same FMC type connector, but have you compared physical pin assignments?

Neither boards documentation lists the other as being compatible.

[Alex02]

I was given the two boards and told to use them together. I thought the person who gave me them would have checked the compatibility before doing so. Thank you for your response @ak6dn.

[FvM]

@ak6dn All FMC cards on the market can be expected to be in many ways pin compatible with the C10GX eval board as far as they follow the manufacturer independent open FMC standard. But there may be nevertheless incompatibilities in detail.

@Alex02 Did you try to set S5.1 to ON to disable the FMC-JTAG chain? Review the Board user manual for details.

If it's not the JTAG chain, there may be a problem of shorted power supplies, although this should never happen if the Xilinx board is designed according to the FMC standard.

Frank

[Alex02]

@FvM Thank you so much! Switching S5.1 worked. It seems the FMC was intercepting the JTAG chain.

[AqidAyman_Intel]

Hi Alex,

I’m glad that your question has been addressed. If you have a new question, feel free to open a new thread to get support from the experts.

Thank you.

[alexforencich]

From looking at the schematic, it looks like you could probably also put a jumper on J5 between pins 6 and 7 to close the JTAG chain.

Schematic: https://www.xilinx.com/content/dam/xilinx/support/documents/boards_and_kits/xtp078.pdf