Problem in compiling verilog code for EMP7064

[ArjunGoel]

Hello,

We have a verilog code which we build on Atmel ProChip Version 5.0 for ATF1504AS (5V and 44pin TQFP). Same is attached as "Atmel.zip".

The output file is a .jed and we were of the opinion that burning this same code in Altera EMP7064 (5V and 44pin TQFP) will give us the same results, but it does not.

Now, we have tried to complie our verilog code in Quartus 13.0sp1 and we get a few warnings. Please see attahced screenshot "Altera-1.jpg" and "Altera-2.jpg". The code is attached as "Altera.zip".

We are unable to understand the issue. The CPLD, when used in the application, performs its functions incorrectly. Please help us rectify this.

[sstrell]

The warnings indicate no timing constraints.  You didn't add your .sdc files in the timing analyzer settings (they don't appear in the .qsf file).  As for the functionality, what is the error/failure you are seeing?

[ArjunGoel]

Hello,

The function of this code is to generate deadtime between PWM pulses. The error we face is that duty cycle of the PWM signal has changed.

The output of Quartus is a .pof file and the output of ProChip (from Microchip/Atmel) is a .jed file. We have a tool to convert a .pof file to a .jed file. We have used this tool and converted the .pof file, which is giving issues in the Intel/Altera CPLD, to a .jed file for Microchip/Atmel CPLD and it works perfectly.

We have no idea what a .sdc file is and how to generate one. Is it possible to connect with you via Upwork or anyother platform so that you can help us get this code working?

[sstrell]

.sdc files define timing constraints for your design to guide the Fitter during place and route.  Your design may be failing timing, which might explain why it's not working.  Take a look at the appropriate timing analyzer user guide here:

https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-software/user-guides.html

Also, your flipflop design is not the proper implementation of a register so they are getting implemented as latches, which can also cause timing issues.  See the Design Recommendations user guide at that same link for recommendations on how to properly code for registers.

[VenTingT]

From your flip flop design shown in the RTL viewer in the Screenshot_FF.jpg, the input (D) of the flip flop needs to connect to an input port or output of another flip flop in order to get timing analysis. It should not connect to a logic “1” otherwise no timing analysis can be performed.
Here is an example of the SDC file. You need to get the measured (max & min) input delay and output delay to set their values inside the SDC file to meet the timing requirements and constrain all paths. After that, you need to add the SDC file to the design. For other warnings, you may right click it > help to see its details.

Another suggestion is, you may use the built-in PLL (Phase-Locked Loop) function to create clock, it is much easier and organized. Then, instantiate the PLL in your top level module.

[SyafieqS]

Arjun,

Is the suggestion above helpful?

[SyafieqS]

Let me know any update on this

[ArjunGoel]

Hi,

Thank you for your response but I have no idea what any of this is. No one in my company knows anything about CPLD or Verilog. We wrote this code on Atmel with the help of youtube and other websites. We have floated a contract for this on Upwork and only when it is resolved I will be in a position to let you know if this worked or not.

[SyafieqS]

Arjun,

Understood. Since you are gonna take sometime to work on this. I will put this to close pending and you may reopen and create new case query for assistance.