I am not seeing the CONFIG_DONE signal go high from the Cyclone 10 FPGA when programming in PS mode from STM32 CPU.
The nSTATUS pin toggles as expected after we toggle the nCONFIG pin, and does not go low to signify an error during programming.
DCLK is 4Mhz.
The programming file used in .rbf generated from Quartus Prime 17.0.0 SJ lite version. Note I can successfully program the device with our design using JTAG.
I would appreciate any advice.
Try reversing the order in which you playback the bits of each byte - perhaps the most likely.
Slow the clock further. More importantly ensure the data is setup sufficiently ahead of the clock edge. (A lack of errors - assuming the bit order is correct - suggests the clock-data relationship is probably fine.) Nevertheless, try clocking data in on the other edge.