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Hi,
I`ve recently received a DE1-SoC with a Cyclone V 5CSEMA5F31C6N. I've tried program it by three different Quartus versions (13.0sp1, 13.1 -web edition- and 15.1-prime lite edition- ) and i've found two problems: 1.- It takes too much time to compile. (5 minutes to compilate an AND gate). 2.- When I use the programming tool, y get ready my .sof file as Users Guide says, but when i click "Start" button, i get the "Failed" message at the progress bar. I've tried to program a .jic file instead of the .sof file, but i've got the same result. Cheers, F PD: To discard possibilities, i have USB drivers correctly installed, and my PC works correctly when programing Cyclone II (DE2).- Tags:
- Cyclone® V FPGAs
- soc
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1) 5 min is normal time.. Have you tried to create SDC file with constraints? Without SDC it try to maximize frequency (1ghz default) and fail.
2) Bad sign.. what message do you get into processing / system output window? Have you set DIP switch correctly?- Mark as New
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1) i'll look to the SCD file constraints.
2) Looking at the processing / system output window, i realized that there was a problem of the JTAG id. That was caused because I was switching the elements in the diagram block which appears in the programming tool, so it coudn´t detect the device. Now, I can program it normally. Thank you very much.- Mark as New
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Hi,
i have a same proleme like you .i work with the same carte (cyclone V 5csema5f31c6n) .but when i would like to choose the id of my cyclone i have just 5csema5f31c6 without n. so the result of programming is always "failed" can you help me please :confused:- Mark as New
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Bonjour tous le monde .
je fais appel à vos connaissances, je voudrai implémenter une image Sur FPGA , je travail sur Quartus. mon idée est la suivante : utiliser un fichier .mif ou je stocke mon image. et j’utilise ce fichier dans une Ram. Alors je cherche un code que me permet de binariser une image RGB n'importe matlab ou vhdl l'important le résultats soit des 0 et des 1 pour la stocker mon fichier MIF. Voila un petit code que j'ai trouver sur net mais ça n'a pas marché %mcode to create a mif file src = imread('lena.jpg'); gray = rgb2gray(src); [m,n] = size( gray ); %size od your picture N = m*n; %your ram or rom depth? word_len = 8; data = reshape(gray, 1, N);% reshape you picture's data fid=fopen('gray_image.mif', 'w'); % open mif file fprintf(fid, 'DEPTH=%d;\n', N); fprintf(fid, 'WIDTH=%d;\n', word_len); fprintf(fid, 'ADDRESS_RADIX = UNS;\n'); fprintf(fid, 'DATA_RADIX = HEX;\n'); fprintf(fid, 'CONTENT\t'); fprintf(fid, 'BEGIN\n'); for i = 0 : N-1 fprintf(fid, '\t%d\t:\t%x;\n',i, data(i+1)); end fprintf(fid, 'END;\n'); % prinf the end fclose(fid); % close your file merci d'avance .- Mark as New
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--- Quote Start --- Hi, i have a same proleme like you .i work with the same carte (cyclone V 5csema5f31c6n) .but when i would like to choose the id of my cyclone i have just 5csema5f31c6 without n. so the result of programming is always "failed" can you help me please :confused: --- Quote End --- Perhaps the following may help. A small integration to both the DE1-SoC User manual (sect. 3.2, pp. 16-18) and the University Program tutorial (Quartus_II_introduction, sect. 9.2, pp. 33-34) is necessary, to let the Programmer not fail the JTAG programming of the FPGA. Figure 3.5 in the DE1-SoC User manual displays the 5CSEMA5 device at the end of the JTAG chain but, after having loaded the .sof file, this device should be replaced by the 5CSEMA5F31 device, as in Figure 3.8 and in the tutorial Figure 41. It actually happens that the latter device is appended to the JTAG chain, but the 5CSEMA5 device is not replaced... pressing the Start button leads to failure (see top-right progress window). Solution: delete the 5CSEMA5 device from the JTAG chain, before pressing the Start button.
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I have the same problem, the thing is that I already did the steps you give but still stays in "Failed" in the progress bar. The device is already replaced with the 5CSEMA5F31. What more can I do?
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Worked 3 days through this. I got mine to work in Windows 11 and Linux Mint. The latter with a slight fpga switch reconfiguration step worth noting. Not sure it's necessary but worked for me. Good luck!
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Hi,
We sincerely apologize for the inconvenience caused by the delay in addressing your Forum queries. Due to an unexpected back-end issue in our system, your Forum cases, along with others, did not get through as intended. As a result, we have a backlog of cases that we are currently working through one by one.
Please be assured that we are doing everything we can to resolve this issue as quickly as possible. However, this process will take some time, and we kindly ask for your patience and understanding during this period. The cases will be attended by AE shortly.
We appreciate your patience and understanding, and we are committed to providing you with the best support possible.
Thank you for your understanding.

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