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Altera_Forum
Honored Contributor I
830 Views

Problem with ALTCLKCTRL module and outputs from two different PLLs in Cyclone III

Hello! 

I'v got a Cyclone III device EP3C16U256. And i have got a two external clock signals 10 MHz and 30 MHz (they are connected to dedicated clock pins on different sides of FPGA). I want to make 120 MHz clock from 10 MHz clock and 120 MHz clock from 30 MHz clock. And i want to dynamicaly switch between them (120 MHz from 10 MHz and 120 MHz from 30 MHz). 

 

I wrote this code: 

... /*** PLL from 30 MHz to 120 MHz ***/ omsp_pll omsp_pll_inst ( .inclk0 ( mclk ), .c0 ( internal_ss_clk ) ); /*** PLL from 10 MHz to 120 MHz ***/ sync_pll sync_pll_inst ( .inclk0 ( sync_clk ), .c0 ( sync_ss_clk ), .locked ( sync_pll_locked_sig ) ); /*** ALTCLKCTRL module ***/ clk_mux clk_mux_inst ( .clkselect ( ss_clk_select_sig ), .inclk0x ( internal_ss_clk ), .inclk1x ( sync_ss_clk ), .outclk ( ss_clk_sig ) ); ...  

 

And i have an error in Quartus (Quartus II 64-Bit Version 13.1.0 ):  

 

--- Quote Start ---  

Error (15669): inclk port of Clock Control Block "clk_mux:clk_mux_inst|clk_mux_altclkctrl_uhi:clk_mux_altclkctrl_uhi_component|clkctrl1" must be driven by 1 PLLs but is driven by 2 PLLs 

Info (15670): Clock Control Block is driven by PLL "omsp_pll: omsp_pll_inst|altpll:altpll_component|omsp_pll_altpll:auto_generated|pll1" 

Info (15670): Clock Control Block is driven by PLL "sync_pll:sync_pll_inst|altpll:altpll_component|sync_pll_altpll:auto_generated|pll1" 

--- Quote End ---  

 

 

 

How can i solve this problem?
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2 Replies
Altera_Forum
Honored Contributor I
48 Views

Refer to Figure 5-1 'Clock Control Block' - page 5-5 - in chapter 5 of the 'cyclone iii device handbook (https://www.altera.com/literature/hb/cyc3/cyclone3_handbook.pdf)'. 

 

Unfortunately, in Cyclone III at least, you're going to need an external loop, fed from one of your PLL outputs to a dedicated clock input pin associated with the Clock Control Block you're using. The Control Block is limited to using two (of the five available) clock outputs from a single PLL. There's no routing to allow a feed from a second PLL. 

 

Cheers, 

Alex
Altera_Forum
Honored Contributor I
48 Views

 

--- Quote Start ---  

Refer to Figure 5-1 'Clock Control Block' - page 5-5 - in chapter 5 of the 'cyclone iii device handbook (https://www.altera.com/literature/hb/cyc3/cyclone3_handbook.pdf)'. 

 

Unfortunately, in Cyclone III at least, you're going to need an external loop, fed from one of your PLL outputs to a dedicated clock input pin associated with the Clock Control Block you're using. The Control Block is limited to using two (of the five available) clock outputs from a single PLL. There's no routing to allow a feed from a second PLL. 

 

Cheers, 

Alex 

--- Quote End ---  

 

 

Thank you very much for the detailed answer!