Problem with ALTGX - rx_dataout drifting

[Altera_Forum]

Hi all. 

 I have a problem with ALTGX core in Arria II GX. I configure it in 8-bit mode (receiver + transmitter) and manual word alignment mode. Then, i'm try to model it in Modelsim.  When i enable serial loopback option, receiver work properly - it fine sync'd and transmit/receive data (counter).  But. When i try to send data to receiver manually (by testbench), the rx_dataout port have "drift". It circullary shifts left with some period. I can't understand - why?  http://www.alteraforum.com/forum/attachment.php?attachmentid=4900&stc=1&d=1319188823

[Altera_Forum]

Solved. 

The problem was been in testbench: 1. ALTGX transceivers was clocked from ref PLL. 2. Checker logic in testbench was clocked from another PLL (or from generated clock). 3. At simulation time, the phase calculation error occured thah result in incorrect latching of ALTGX_RX output in checker logic.  I solved this problem by clocking all testbench components from one PLL. In addition, this incorrect behavior also arise at some input frequencies on PLL.