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Altera_Forum
Honored Contributor I
2,028 Views

Problem with Quartus and PIN plan (EP4CE6)

I am currently working with FPGA as part of a course at the university. At the university we use Terasic Altera Cyclone III EP3C16 Development & Education boards, I am quite familiar with it, I can find it in Quartus, have user manual with all of the pins and everything works fine... 

 

However, I recently bought an FPGA from Aliexpress in order to exercise at home. I am not completely sure which model it is but it should be hynix EP4CE6 with Cyclone IV EP4CE6E22C8N. I have two problems with it: 

 

1. I cannot find the following chip in Quartus (there is only Cyclone IV EP4CE6E22C8, but not Cyclone IV EP4CE6E22C8n

2. I cannot find the user manual with all of the pins for LEDs, switches, BTNs, 7SegDisplays... 

 

Here is how the board and chips look like: 

https://preview.ibb.co/grRnRd/IMG_2567.jpg https://preview.ibb.co/b7hSRd/IMG_2571.jpg  

https://preview.ibb.co/jMO1md/IMG_2572.jpg
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6 Replies
Altera_Forum
Honored Contributor I
171 Views

Googling for 'Storm_IV_XX_v2.0' did not find much, just this: https://www.eevblog.com/forum/microcontrollers/mysterious-fpga-board-with-vga-output/ 

(https://www.eevblog.com/forum/microcontrollers/mysterious-fpga-board-with-vga-output/

Read those blog entries, there is a pointer provided to some software that someone found. 

 

The one key comment is: "The eBay seller answered, said the supplier doesn't provide technical support." 

 

Also, ep4ce6e22c8 vs ep4ce6e22c8n is inconsequential. The final -N indicates a lead-free package; no -N suffix is leaded. Lead-free vs leaded makes no difference to Quartus; only matters when you are soldering PCBs.
Altera_Forum
Honored Contributor I
171 Views

 

--- Quote Start ---  

Read those blog entries, there is a pointer provided to some software that someone found. 

--- Quote End ---  

 

The posted pdf schematic should have the pinout information you are missing.
Altera_Forum
Honored Contributor I
171 Views

Thank you for your replies. The link ak6dn provided helped me a lot with finding the PIN assignments. However, there are more problems which I encountered now. 

 

1. When I tried to test some scheme, I connected the board with USB blaster on the port JTAG (not AS), installed driver from C:/altera folder and tried to transfer my scheme but got "Failed". 

https://preview.ibb.co/jC7i1d/problem.png  

 

2. I am not sure how to use 4 SevenSegment displays which are available on the board since there are PIN assignments for only one of them. 

https://image.ibb.co/iCZ5gd/7seg.png  

https://preview.ibb.co/df0NSJ/segled.png  

I see this option to select which display to use but how to use all of them at the same time?
Altera_Forum
Honored Contributor I
171 Views

 

--- Quote Start ---  

Thank you for your replies. The link ak6dn provided helped me a lot with finding the PIN assignments. However, there are more problems which I encountered now. 

 

1. When I tried to test some scheme, I connected the board with USB blaster on the port JTAG (not AS), installed driver from C:/altera folder and tried to transfer my scheme but got "Failed". 

https://preview.ibb.co/jC7i1d/problem.png  

 

2. I am not sure how to use 4 SevenSegment displays which are available on the board since there are PIN assignments for only one of them. 

https://image.ibb.co/iCZ5gd/7seg.png  

https://preview.ibb.co/df0NSJ/segled.png  

I see this option to select which display to use but how to use all of them at the same time? 

--- Quote End ---  

 

 

WRT (1), I suspect the settings of switches 1-4 in the little red dip switch pack may apply here, to set the boot/config mode you want to use. The schematic, along with the FPGA user manual, will tell you how to set the switches to use JTAG mode for configuration. 

 

WRT (2), the four seven segment displays have been implemented in multiplexed mode, so they use only 4+7=11 total I/O lines, instead of 4*7=28 total I/O. So to use all four displays, your FPGA will have to implement the 4:1 segment multiplexing logic within your code. It is not really that hard to do. Here is a simple example using a microprocessor and C code: http://embedded-lab.com/blog/lab-11-multiplexing-seven-segment-led-displays/ You just need to do it in verilog and/or vhdl.
Altera_Forum
Honored Contributor I
171 Views

1. I thought that I can use those switches for input in my schemes, not JTAG settings since this is written in schematic: 

https://image.ibb.co/fyKG4y/Screen_Shot_2018_07_02_at_2_16_57_AM.png  

 

And this is the only thing I found about JTAG and AS: 

https://image.ibb.co/kD89Py/Screen_Shot_2018_07_02_at_2_17_06_AM.png  

 

2. Thank you very much for this, I understand how to do this and it will be an easier problem to solve when I put everything into place to work properly.
Altera_Forum
Honored Contributor I
171 Views

 

--- Quote Start ---  

1. I thought that I can use those switches for input in my schemes, not JTAG settings since this is written in schematic: 

https://image.ibb.co/fyKG4y/Screen_Shot_2018_07_02_at_2_16_57_AM.png  

 

And this is the only thing I found about JTAG and AS: 

https://image.ibb.co/kD89Py/Screen_Shot_2018_07_02_at_2_17_06_AM.png  

 

2. Thank you very much for this, I understand how to do this and it will be an easier problem to solve when I put everything into place to work properly. 

--- Quote End ---  

 

 

Ok, so it looks like those four switches are just for user data input, have nothing to do with configuration. 

 

Re: configuration, your device is probably setup for AS configuration from a board EPCS-compatible flash EEPROM (the MSELx pins will set this up). 

 

However, JTAG configuration should be able to override this and you should be able to download a .sof file directly to the FPGA sram configuration. Since that is not working, I recommend using the programmer software JTAG debugger tools to validate your JTAG interface is working correctly. Under the programmer 'Tools' menu there is the 'JTAG Chain Debugger' selection you can use to validate that basic JTAG is working, or not.
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