Problem with clock on altera FPGA de2 board

[Altera_Forum]

Hi altera

I am on my first ever project with a Altera FPGA de2 board, and are

also new to vhdl.

I have encountered a problem i hope u all can help me with.

I am trying to implement a systolic system for modular exponentaion,

using the montgomery modular exponentation algorithm. How to design

this, i don't need help with, my problem is a tecnical vhdl/quartos II

problem.

My problem is i have 2 external clock signals (which is pins on the

board, since i want to control the clock myself), 1 clock for running

the system, and 1 clock for loading registers with the right data,

before the system is going to start.

When i try to compile i get some warnings:

the 2 warnings i have trouble with is those related to the clock:

Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew

Info: Detected gated clock "Zv[1]~8" as buffer

Info: Detected gated clock "Yv[1]~8" as buffer

Info: Detected ripple clock "Shiftreg:ShiftE|S[8]" as buffer

Warning: Circuit may not operate. Detected 8 non-operational path(s) clocked by clock "Clock2" with clock skew larger than data delay. See Compilation Report for details.

I have searced forum for information about this, and have found that it is a good idea to use clock enable (although i don't know how to use this), or setting clock assignment manually (for this i don't know either how to setup). how can i, when using my clock that are assigned to 2 pins, get past this clock scew problem? please help... i'm a noob at this, and need help.

Regards JJA

My code is attached