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Hi,
I am fairly new to using Quartus. (using version 8.0) I have a project that Successfully compiles in the GUI. However, when I try to use quartus_map I get the following errors: --- Quote Start --- $ quartus_map fec_dsp_interface_pkg_top --source fec_dsp_interface_pkg_top.qpf --family=CYCLONEIII Info: ******************************************************************* Info: Running Quartus II Analysis & Synthesis Info: Version 8.0 Build 231 07/10/2008 Service Pack 1 SJ Full Version Info: Copyright (C) 1991-2008 Altera Corporation. All rights reserved. Info: Your use of Altera Corporation's design tools, logic functions Info: and other software and tools, and its AMPP partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Altera Program License Info: Subscription Agreement, Altera MegaCore Function License Info: Agreement, or other applicable license agreement, including, Info: without limitation, that your use is for the sole purpose of Info: programming logic devices manufactured by Altera and sold by Info: Altera or its authorized distributors. Please refer to the Info: applicable agreement for further details. Info: Processing started: Tue Jan 27 15:57:19 2009 Info: Command: quartus_map fec_dsp_interface_pkg_top --source=fec_dsp_interface_pkg_top.qpf --family=CYCLONEIII Warning: Using design file fifo_controller.vhd, which is not specified as a design file for the current project, but contains definitions for 3 design units and 1 entities in project Info: Found design unit 1: fifo_controller_pkg Info: Found design unit 2: fifo_controller-behaviour Info: Found entity 1: fifo_controller Error (10481): VHDL Use Clause error at fifo_controller.vhd(93): design library "work" does not contain primary unit "dsp_register_pkg" File: fifo_controller.vhd Line: 93 Error (10800): VHDL error at fifo_controller.vhd(93): selected name in use clause is not an expanded name File: fifo_controller.vhd Line: 93 Error (10481): VHDL Use Clause error at fifo_controller.vhd(94): design library "work" does not contain primary unit "dsp_status_register_pkg" File: fifo_controller.vhd Line: 94 Error (10800): VHDL error at fifo_controller.vhd(94): selected name in use clause is not an expanded name File: fifo_controller.vhd Line: 94 Error (10481): VHDL Use Clause error at fifo_controller.vhd(95): design library "work" does not contain primary unit "constants" File: fifo_controller.vhd Line: 95 Error (10800): VHDL error at fifo_controller.vhd(95): selected name in use clause is not an expanded name File: fifo_controller.vhd Line: 95 Error: Quartus II Analysis & Synthesis was unsuccessful. 6 errors, 1 warning Error: Peak virtual memory: 173 megabytes Error: Processing ended: Tue Jan 27 15:57:20 2009 Error: Elapsed time: 00:00:01 Error: Total CPU time (on all processors): 00:00:01 --- Quote End --- Any ideas would be appreciated as I am working to develop scripts around Quartus. Thank you, TomLink Copied
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Why are you using all those command line arguments? The qsf file (which the qpf points at) has all the settings that you need, just run
quartus_map <projectfile.qpf> in your script, (minus the <>)- Mark as New
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Thank you, this seems to fix that. I was going verbatim from the Altera Command-Line Scripting documentation.

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