Problems with design example Low Latency Ethernet 10G MAC Intel FPGAIP

[eamun1]

I've created the Design example base on the Low Latency Ethernet 10G MAC Intel FPGAIP, with the following parameters

I open the project and suscessfully compile it, I try to run the simulation as in the user guide explains , I'm using modelsim:

But I got an error message, 

Attached the log file, How could be the problem? the folder has the corresponded permissions, 

[Deshi_Intel]

HI,

I can't see the pic attachment in this forum. The only attachment available is the log file only.

1. May I know are you using Arria 10 or Stratix 10 FPGA for the sim run ?
2. Looking at your sim log file. The error is complaining it can't find certain design files in your Quartus project folder. Have you verified the design files is there in folder or missing ?
3. The other thing that I noticed is you are using Quartus v19.1 pro but pair with Modelsim 10.5b. Based on Quartus v19.1 Pro release note,you should be using Modelsim 106d instead to avoid sim tool compatibility issue.
4. Another possibility that I can think off is maybe either your Quartus project or Ethernet example design is corrupted.

My debug suggestion is :

• Create a new Quartus project and generate new Ethernet example design
• Then run sim again using Modelsim 10.6d as your example design is generated from Quartus pro v19.1

Thanks.

Regards,

dlim

[eamun1]

Hello, I will try to attach again the picture,

on the other hand I tried your solutions, I've created a new project example and ran it with the 10.6d with same results,

[eamun1]

[Deshi_Intel]

HI,

Thanks. I can see your attachment image now.

• Can you confirm are you using Cyclone 10 GX FPGA or which FPGA ?
• Also, can you share screen shot of the Ethernet "IP" page instead of "example design" page. It's good to know what setting that you configured

So, Modelsim 10.6d still failed ya.

• Have you looked into the sim log error message to locate the design files to see they are really missing in project folder or so ?
• Btw, I also found below known issue in the past. You can try shorten your Win Quartus project folder path and see
  • https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/hsio/2019/error---vlog-7--failed-to-open-design-unit-file-------------rtl-.html

Thanks.

Regards,

dlim

[eamun1]

Yes, I'm using 10GX220YF780 .

I changed the path to a shorter one and it seems to work!, but now the simulation stops in a different point. See log attached

[eamun1]

I attached the IP configurations aswell

[Deshi_Intel]

HI,

It's good to know that sim can compile the design successfully now after shorten the design folder path but looks like you bump into new sim halted issue.

I dig into KDB link again and found out below link. I highly encourage you to checkout the KDB link from time to time as well to find out some clue that maybe able to help resolve your issue.

• https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/ip/2020/why-does-the-low-latency-ethernet-10g-mac-intel--fpga-ip-generat.html

Looks like there could be some issue with sim design generated from older Quartus version.

Kindly use latest Quartus v19.4 to regenerate new sim project again and give it another try.

Thanks.

Regards,

dlim

[eamun1]

With Quartus v19.4 I have the same results as before, attached file

[Deshi_Intel]

Thanks for feedback.

Let me test out the v19.4 example design from my side as well.

Regards,

dlim

[Deshi_Intel]

Hi,

I just gotten feedback from Intel Engineering team.

Sim run with Modelsim Intel FPGA may take 8 to 12 hours to complete.

• May I know how long did you run the sim ? Else I suggest you to rerun the sim again
• I will also try run the sim from my side overnight to check the result

If you need faster sim run time, then the better option will be to use Modelsim SE version instead.

Thanks.

Regards,

dlim

[eamun1]

Hello, thank you for your help, I ran it about an hour, I stopped manually since I thought it was frozen. I will try to run the simulation again. When you talk about Modelsim SE you mean to Stater Edition? Because that is the one I have install already

[Deshi_Intel]

HI,

Good luck in trying again. My sim run is in progress as well. I will check the result in tomorrow.

Nope, I am not referring to starter edition. That's the Intel FPGA free edition with even lower performance.

I am referring to Special Edition (SE). More powerful and expensive edition. You can checkout below link.

• http://read.pudn.com/downloads82/doc/project/317719/compare.pdf

For further detail, you may want to consult back Mentor Graphic.

Thanks.

Regards,

dlim

[Deshi_Intel]

HI,

I let sim run overnight. Just checked the sim log and it's passing after around 7 hours run.

The actual sim run time may vary on your side but hopefully thing works out on your side as well.

Thanks.

Regards,

dlim

[eamun1]

Hello, I suscessfully ran the simulation after 4 hours. !

Thanks for your support!

Now I can see  Statistics on the cmd but is there any other output like waveforms or so on. How can I interact with the simulation results?

[Deshi_Intel]

HI,

Good. Things is working on your side as well.

From my end, I did able to see the Modelsim waveform window pop up as well but I am not sure when it pop up.

Why not you let the sim run finish at your end first to see whether the Modelsim Waveform Window pop up or not ?

Thanks.

Regards,

dlim

[eamun1]

Hello, the windows waveform did not pop-up, I re-ran the simulation just to be sure. The result says Simulation PASSED so it ends but no waveforms shown

[Deshi_Intel]

Hi,

This is weird.

Btw, did you click "NO" on the sim pop up windows when it asked you whether do you want to finish or complete the sim after sim passed ?

Also, couple of things that you can check in example design folder

• LL10G_10GBASER\simulation\ed_sim\mentor

1. Do you see the sim waveform file (vsim.wlf) ?
2. Do you see msim_wave.do file ? This is the script to add design signals to Modelsim Waveform
3. You can also check tb_run.tcl script to make sure it execute the wave.do file. The command is just do wave.do

Ultimately, you can also edit the tb_run.tcl script to stop auto run (comment out do wave.do and run -all) to manually run the command in Modelsim console to test it.

Thanks.

Regards,

dlim

[eamun1]

Hello, no there is no pop up windows i didn't click anything.

1.Yes I see it

2. yes, I see it

3. this is the script:

# Add waveform

do $tb_top_waveform

# Run the simulation

run -all

How i have to modify it to run it manually?

[Deshi_Intel]

Hi,

If you can see the waveform output file (vsim.wlf) generated in your sim project, you are all set.

I am guessing you didn't enable or pull out the sim waveform windows during sim run. Not sure why the sim waveform window doesn't pop up automatically.

Now, you can go back to Modelsim

• File -> Open -> vsim.wlf
• It should bring you to sim run windows
• Right click on the tb_top -> add to -> wave -> all items in region
• The sim waveform window will pop up with all signals activity captured

Thanks.

Regards,

dlim

[Deshi_Intel]

Hi,

It's been a while since I last heard from you.

Hopefully your modelsim is working as expected now with my debug suggestion.

For now, I am setting this case to closure.

Thanks.

Regards,

Deshi