Process involved in loading POF file from flash

[Altera_Forum]

I am currently in the process in trying to make a custom board that has a FPGA. One of the things I want it to do, is to be able to power on and load a POF file without having to be programmed through a computer. I can do this on the development boards using the parallel flash loader megafunction component. However, I'm confused in the steps I need to follow in order to make this happen in my custom board.  

 I have the CFI flash device and I have the JTAG pins and I have the FPGA, but I don't understand how upon applying power the FPGA will try to grab the programming file from the flash memory. I know that the dev kits all use the CPLD to do this function, so do I need to use a CPLD as well?  This is my first time trying to make a custom board and I've had trouble finding app notes that talk about this specifically. I'm assuming that getting the programming file to the flash memory is the same process described in the guide under programming the flash device. All the information I've read seems to lead me in the direction that I would need a CPLD to do this but I haven't been able to find a black and white answer explaining this process.

[Altera_Forum]

I can answer part of your question... If you are loading the programming file from Flash, the FPGA cannot do it directly. You will need an active part to do that. You can use a MAX II, a CPU, a PIC... I have used a processor in the past to load the FPGA but I have never used the loader megafunction.

[Altera_Forum]

The loader function would not load the file into the fpga, that is just used to load the file into the flash device from the FPGA.  

 Regarding your answer, what is the easiest/cheapest way to implement that and are there good example projects or is it as simple as writing a driver for an LCD. For example, all that is needed is code that tells the flash to write to the FPGA configure pins for x amount of address locations and then wait for the config done pin to tell it everything went smooth otherwise rewrite?

[Altera_Forum]

did you take a look at the PFL User Guide? i think your questions are pretty well covered, it mentions that typically the PFL is run in a CPLD but it can be run in an FPGA. its usually used in a CPLD which has "instant on" capability. the CPLD can go out and read the CFI flash, and send this data to the FPGA via FPP or PS programming. you shouldn't have to write much code 

 the recent development kits are using this type of configuration, check out the schematics and design files. Cyclone III LS and Stratix IV GX are two boards i know use a MAX II and PFL

[Altera_Forum]

to load the CFI flash, the kits are using a Nios II with CFI flash controller, and the Nios II Flash Programming tools to load over JTAG to the FPGA. you can also write to the flash using the MAX II via JTAG and the PFL 

 if you search Altera's website for: pfl pdf you can find the user guide as well as a couple of application notes

[Altera_Forum]

The last part you mentioned is confusing me but I might just be missing something. When I loaded my pof file into the dev board all I did was program the pfl into the fpga and then I added my CFI flash device and then added the pof file. Is this process using the MAX II as well?  

 Otherwise I only see the MAX II being used as a way to load the FPGA via a PFL that is inside the device more or less taking the data from flash to FPGA instead of FPGA to flash.

[Altera_Forum]

in this case you wrote to flash using the FPGA PFL, but when the board was rebooted, the MAX II was actually the PFL which read the CFI and configured the FPGA 

 it is a bit confusing

[Altera_Forum]

Alright thanks for the clarification, I think I understand it now.

[Altera_Forum]

You didn't mention the involved FPGA at all. If it's supporting AP configuration mode (e.g. Cyclone III, except some low pin count types) you don't need a MAX II, the flash memory can be intefaced to the FPGA directly.

[Altera_Forum]

ah yes, Active Parallel. thanks