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HBhat2
New Contributor II
347 Views

Programming EPCQ from External processor

Hi,

We are targeting Arria 10 GX & we want to use 3 EPCQ devices to contain 3 different Binaries controlled by nCSO [0:2] lines in the custome hardware design.

Also, in the custom hardware, there is an NVIDIA processor is present. In the product version we want to update the EPCQ content from the processor instead of updating the EPCQ content (jic) over JTAG.

We came to know that there is an IP called  " remote update IP" and that could be used for updating EPCQ. However I am not clear with regards to the interface between Processor & FPGA. Is it possible to update over SPI or PCIe interface from External processor?

I have attached the system level block diagram for your reference.

With Regards,

HPB

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9 Replies
JohnT_Intel
Employee
330 Views

Hi,


The remote update IP is only use to remotely reconfigure the FPGA with the new bitstream. It cannot be use to update the EPCQ device.


You use any interface connected to the FPGA where the interface IP need to communicate with the Generic Serial Flash Interface IP (https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-gen-sfi.pdf) in order to update the EPCQ flash.


HBhat2
New Contributor II
310 Views

Hi,

 

Thanks for the reply. With respect to using "Generic Serial Flash Interface IP", I have couple of questions.

1) Do you have any source code / reference design  to interface the External processor to JTAG UART module of FPGA?

2) We are not  planning to use Quartus programmer or any Intel tools from Host PC to update the EPCQ device. Is it possible to update without Quartus programmer or Nios console to interface between External processor & FPGA .

 

With Regards,

HPB

JohnT_Intel
Employee
306 Views

Hi,


You can refer to https://fpgacloud.intel.com/devstore/platform/18.0.0/Standard/generic-serial-flash-interface-intel-f... which is a reference design for Cyclone V E. You can migrate the design to Arria 10.


HBhat2
New Contributor II
293 Views

Hi,

Thanks for the quick reply. I downloaded & understood the example design on high level.

I understood that the host interface is through JTAG. 

As I mentioned previously, we are connecting the FPGA to external processor without JTAG. So, we do not want any dependency of tools like USB blaster/Quartus programmer/Nios Console.

This requirement is for the field upgradable option of Arria 10 based product. 

Our requirement is the external processor must have a standard interface like UART/SPI and the external processor must be able to send the new Flash content through SPI/UART to FPGA. The FPGA must then send those contents to EPCQ flash.

To support above requirement, flash interface IP is fine in the flash side. But, the way FPGA receives the flash content through JTAG is the concern. 

How to send the JIC content from External processor to FPGA over UART/SPI?

What file format of JIC content must be sent by the external processor to FPGA?

With Regards,

HPB

JohnT_Intel
Employee
291 Views

Hi,


I would recommend you to send rpd file rather than jic file. You can modify the design example to UART or other interface.


You can also refer to https://fpgacloud.intel.com/devstore/platform/15.1.0/Standard/remote-system-upgrade-over-uart-based-... which performed remote update and you can add the Generic Serial Flash IP in order to update the flash content.


HBhat2
New Contributor II
288 Views

Hi,

Thanks for the real time answer. We will check on rpd format & how we can use UART/SPI interface to send that format from external processor.

Just one concern with remote update. If at all remote update failed due to unwanted scenarios like external processor shutdown or FPGA shutdown in the middle of remote update, whether Flash will contain previous image until new image is written completely or we need to take this scenario by creating 2 images in the EPCQ memory (one image is factory image & other is updated image)?

With regards,

HPB

JohnT_Intel
Employee
287 Views

Hi,


I would recommend that you retain the factory image that will not be change and only update the application image. So if there is any issue happen during the application image update then it will always revert back to factory image until you update the application image again.


HBhat2
New Contributor II
281 Views

Hi,

Yes, we would like to have 2 images (factory & new image due to update).

Can you share any reference design/ guidelines/document to have 2 images in single EPCQ .

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-gen-sfi.pdf

Above document does not give any info regarding the multiple image in a single flash.

With Regards,

HPB

JohnT_Intel
Employee
278 Views

Hi,


I would recommend you to refer to https://fpgacloud.intel.com/devstore/platform/16.0.0/Standard/remote-system-upgrade-over-uart-based-... where it will provide you the guide how to implement 2 images into single Flash.


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