QSPI slave interface in Cyclone10LP

[MS]

Hi,

in Cyclone10LP I need to implement a QSPI interface to a host MCU (ie. MCU is master, FPGA behaves as slave).

Is there a ready made IP-Core available by Intel?

With the IP-Finder I've got https://www.intel.com/content/www/us/en/programmable/solutions/partners/partner-profile/digital-core-design/ip/dqspi---serial-peripheral-interface-master-slave-with-single--dual-and-quad-spi-bus-support.html as a result. In the docs I'm getting pointed to the Gerneric Serial Flash Interface (https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-gen-sfi.pdf) which seems to not support the slave mode.

Any hints are welcome.

[GuaBin_N_Intel]

There is no slave based QSPI from IP catalog https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_embedded_ip.pdf. This DSPI IP is developed by 3rd party https://dcd.pl/workspace/documentation/alt/dqspi_ds.pdf where you can contact directly them to find out more details you needed.