QSYS - DMA - Clock Bridge

[Altera_Forum]

Hi, 

 I have a PCIe / DMA QSYS project which uses the module SGDMA in MM to ST mode. I'm streaming to a FIFO. I had to export the data source port of the read master so I could tie it to my FIFO. I want the write side of the FIFO to run at the PCI core, 250MHz. In order to accomplish this I had to use a Clock Bridge with two outputs: one output feeds all of the other components in my QSYS design and the other one is exported so I can tie it the write clock of my FIFO. When generating my QSYS, I get the following error.  Error: q_sys_tb.q_sys_inst: q_sys_inst.dma_read_master_1_data_source and q_sys_inst_dma_read_master_1_data_source_bfm.sink must be on the same clock domain, since they're connected.  QSYS generates a BFM for this port which seems to be tied to this error. When I dig in the qsys.v file, I see this instantiation. It has the .clk port tied to the 50MHz clock which feeds the cal_blk_clk and reconfig_gxbclk of the PCIe IP.  q_sys_inst_dma_read_master_1_data_source_bfm (  .clk (q_sys_inst_clkin_50_bfm_clk_clk), // clk.clk  .reset (~q_sys_inst_clkin_50_clk_in_reset_bfm_reset_reset), // clk_reset.reset  .sink_data (q_sys_inst_dma_read_master_1_data_source_data), // sink.data  .sink_valid (q_sys_inst_dma_read_master_1_data_source_valid), // .valid  .sink_ready (q_sys_inst_dma_read_master_1_data_source_ready), // .ready  .sink_startofpacket (1'b0), // (terminated)  .sink_endofpacket (1'b0), // (terminated)  .sink_empty (3'b000), // (terminated)  .sink_channel (1'b0), // (terminated)  .sink_error (1'b0)   What does this mean and how do I fix?   https://www.alteraforum.com/forum/attachment.php?attachmentid=7733    Rob