Qsys HPS SDRAM and peripheral connections

Altera_Forum · ‎12-11-2017

Hi everyone, I'm looking for some help understanding how the HPS IP is used in Qsys and Quartus.

I'm using a Cyclone V SoC with Quartus 17.1, and at the moment I'm trying to just design some simple links between the ARM cores (running Linux) and the FPGA fabric.

I've got that working fine, but I'd like to know why Qsys exports and instantiates so much SDRAM related logic (and IO for any enabled peripherals). There's over 3000 lines of parameters in the .qip file, and over 30 tcl/verilog files mostly all relating to the SDRAM properties. This all then needs to be connected to DDR pins in my top level module. However, since all the SDRAM is HPS-only, and the pinout and pin properties and DDR properties are only set by the preloader, I don't understand why qsys exports it to HDL or what it's meant to be doing in Quartus. If I go in and delete all of the memory connections, all the sdram files, and clean out most of the .qip file, then my HPS IP looks like:


module soc_hps_0 (
        output wire        h2f_rst_n,
        input  wire  h2f_gp_in,
        output wire  h2f_gp_out
    );
    soc_hps_0_fpga_interfaces fpga_interfaces (
        .h2f_rst_n  (h2f_rst_n),
        .h2f_gp_in  (h2f_gp_in),
        .h2f_gp_out (h2f_gp_out)
    );
endmodule

I no longer need to make any top-level connections to HPS IO, and the build time for a simple project goes from 5 minutes to about 40 seconds, which is a nice improvement! The result seems to be completely functional and there are no warnings or errors. What am I missing? Why (does Qsys) bother having Quartus spend a load of time doing SDRAM related work that it will just discard?

I think this is a similar question to https://www.alteraforum.com/forum/showthread.php?t=55380 but at least with the peripheral IO you can disable it in qsys and it won't get exported. I can't find any way to tell qsys to not export the SDRAM stuff.

Cheers