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NShin3
Beginner
563 Views

Qsys/Platform Designer does not generate submodule files when using two Avalon MM Slaves

I have created custom Avalon MM slaves. I want to connect them to a Master.

 

The Qsys/Platform Designer tool does not generate submodule files when more than one Avalon slaves are connected to Avalon Master.

 

It generates all files when using only single Avalon MM slave.

 

Is this a problem with Quartus/Platform designer/Qsys tool or Custom component?

 

Any help is appriciated.

 

 

Image 1: here you can see 1 master and 2 slaves. I clicked "Generate"

avalon mm 1.jpg

 

 

 

Image 2: After copiyng instantiation, getting error while compiling projectavalon mm 2.jpg

 

Image 3: See the time for QIP file(updated) and Submodules folder (not updating)avalon mm 3.jpg

 

 

I am able to complete the design with 1 slave, but cant do with 2 slaves.

 

Any solution ?

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14 Replies
AnandRaj_S_Intel
Employee
120 Views

Hi,

 

Quartus/Platform designer/Qsys tool will generate all the required files.

 

  1. include the .v/.vhd file of your Custom component (Project navigator->files-?add/remove files in the project)
  2. Quartus will update only the required files after changes which also saves the generation or compilation time. However, you can delete the folder/file and regenerate.

 

Regards

Anand

NShin3
Beginner
120 Views

Hello Anand,

 

I followed this process but still have the same problem.

 

Image 1 : Single Avalon MM slave.

-- Submodules folder generated with all sub files.

-- inst file is also generated.

avalon mm 5.jpg

 

 

Image 2 : Two Avalon MM slaves.

-- No Submodules folder generated.

-- No inst file.

-- Only QIP file.

avalon mm 4.jpg

 

 

 

Thanks and Regards,

Niranjan

AnandRaj_S_Intel
Employee
120 Views

Hi,

 

May be due to custom component.

follow the steps from below file.

 

Can you share the project?

 

Regards

Anand

NShin3
Beginner
120 Views

Hi,

 

I followed this same document to create custom components.

Only difference is I am using conduit signals to get data from FPGA modules instead of instantiating inside slave MM interface.

 

I have shared verilog files of master and slaves in the comments below.

 

Thanks and regards,

Niranjan

sstrell
Honored Contributor II
120 Views

Very strange. Do you only have this issue when you connect two or more of the same component to the master? If you connect this custom component and some other component to the same master, does it generate OK?

 

I would try deleting the custom component's _hw.tcl file, and then go through the Component Editor again. It doesn't make sense that one instance works but more than one doesn't.

 

Also, maybe you could post the Avalon interface part of the code for the custom component. Maybe there's an issue with how you've set up the Avalon signaling. It might also be useful to see how you've configured the Signals & Interfaces tab of the Component Editor.

 

#iwork4intel

NShin3
Beginner
120 Views

Hi,

 

Thanks for the suggestion.

I have attached Avalon MM master and two slave Verilog files.

 

Slave : read only, with signals and interfaces

avalon slave fm.jpg

 

 

NShin3
Beginner
120 Views

This is master signals and interface tab with code.

Conduit signals are for Controlling master through FPGA switches.

avalon master.jpg

NShin3
Beginner
120 Views

slave signals and interfaces, with code.

This slave is for write operation only.

avalon slave attenuator.jpg

AnandRaj_S_Intel
Employee
120 Views

Hi,

 

  1. Your Custom component with Avalon MM design is not complete/ correct.
  2. You can use Noss ii or JTAG to Avalon master bridge and check it will generate all the file for any number of slave.

 

Also, refer to Avalon interface specification & template.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_avalon_spec.pdf

https://www.intel.com/content/www/us/en/programmable/support/support-resources/design-examples/intel...

 

Regards

Anand

sstrell
Honored Contributor II
120 Views

You didn't mention that the master was custom as well, but I don't think the master is the issue. However, what is the rest of that warning message you get when trying to generate the system? It's cut off in your screenshot.

 

In your attenuator component, unless it's an error, the address input isn't doing anything since you write the same data to reg0 no matter the address. You could remove the address input to the component.

 

I'd still try going through the component editor again and recreating the _hw.tcl files and saving and regenerating the system.

 

#iwork4intel

NShin3
Beginner
120 Views

avalon slave fm warning.jpg

Warning: Translator master_0_avalon_master_translator failed to match interface master_0.avalon_master

 

-- I tried going through the component editor again and recreating the _hw.tcl files and saving and regenerating the system.

Still same warning same problem.

 

-- For attenuator component which has no effect of address, if i dont use address then how master will identify it ? there should bre address/ location to differentiate with other slave, right ?

 

sstrell
Honored Contributor II
120 Views

With only a single addressable location, you don't need the address signal in the component. You'd still give a unique address in Platform Designer when building a system which would then handle which of multiple slaves to access in the interconnect.

NShin3
Beginner
120 Views

Thanks for this new info.

 

Could you tell more about this warning ?

 

WarningTranslator master_0_avalon_master_translator failed to match interface master_0.avalon_master

 

AnandRaj_S_Intel
Employee
120 Views

Hi,

 

Basically Avalon master translator converts the Avalon-MM master interface to a simpler representation for use in Qsys, for more information refer Quartus user guide.

 

Try to compare the design with Avalone memory-mapper master template.

https://www.intel.com/content/www/us/en/programmable/support/support-resources/design-examples/intel...

 

https://www.intel.com/content/www/us/en/programmable/documentation/zcn1513987282935.html

 

Regards

Anand

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