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Hi , I am trying to create a new component on Qsys using my verilog code in quartus. I am getting some errors [please look over the attachment], I don`t know how to fix it. Please guide me
Verilog code module coun (
LED , // Output of the counter
clk , // clock Input
);
input clk;
output reg LED;
reg out=0;
always @(posedge clk) begin
out <= out + 1;
LED=out;
end
endmodule
I need step-step training please
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Hi,
Image is not clear can you reattach the screen short of the error and interconnect in two image? Regards Anand- Mark as New
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Did you check out the training I highlighted here: https://alteraforum.com/forum/showthread.php?t=58107&p=236429&highlight=#post236429
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