Quartus (19.4), error when auto_global_register_control_signals is set ON

[AEsqu]

Quartus (19.4), error when auto_global_register_control_signals is set ON,

see attached pictures.

[AEsqu]

posted a file.

[AEsqu]

posted a file.

[KhaiChein_Y_Intel]

Hi,

This error is due to either of the reasons below:

1) You created assignments such as location assignments, clique assignments, or Logic Lock region assignments. These assignments forced a group of logic cells into one LAB. However, the group of logic cells cannot be placed in a single LAB. This message can occur when there are too many logic cells to fit in one LAB, or when the logic cells require more signals (such as clock enables) than a single LAB can provide.

2)  You back-annotated the contents of one or more Logic Lock regions with a LAB-level back-annotation instead of LE-level. During the initial compilation (that is, the compilation that produced the results you back-annotated), the Fitter built a legal solution such that all cells could be placed in asingle LAB. However, during the current compilation, the Fitter could not find that solution and so this group of logic cells could be packed together to fit into a single LAB.

3) You imported Logic Lock region assignments from another project into the current project, but the imported assignments require more device resources than are available in the current project. For example, the logic cells that the imported assignments force into a single LAB may require more signals (such as clock enables) than a single LAB can provide. This message can occur if, in the project from which the assignments were imported, the Fitter promoted one of the required signals to a global signal to fit these logic cells into a single LAB. However, in the current project, there are not enough global signals available to perform this promotion. For example, if the entity for which you imported the assignments is instantiated multiple times in the current project, there may not be enough global signals to instantiate those assignments for each instance of the entity in the current project.

You have to check the submessages and fix the error.

Case 1: Remove some of the location, LAB clique, and/or Logic Lock assignments to the cells constrained to lie in one LAB.

Case 2:Back-annotate the design again, but this time choose LE-level back-annotation.

Case 3: Delete back-annotated assignments in the Logic Lock region containing the nodes listed in the submessages.

Thanks.

Best regards,

KhaiY

[KhaiChein_Y_Intel]

Hi,

Do you have any updates?

Thanks.

Best regards,

KhaiY

[AEsqu]

Hi,

I don't use any lock.

See my attached qsf.

[KhaiChein_Y_Intel]

Hi,

Could you provide a non-confidential simple test case that can reproduce the error?

Thanks.

Best regards,

KhaiY

[KhaiChein_Y_Intel]

Hi,

Do you have any updates?

Thanks.

Best regards,

KhaiY

[AEsqu]

Sorry KhaiY,

I'm now busy with our chip validation (the one that was mapped on FPGA before),

If I find time I will do this, but this is not my prio right now.

Have a nice day and stay safe against the COVID 19 disease.

Alex.