Quartus Error (13066): Illegal directional connection from the pin (inout)

[Altera_Forum]

Hello all, 

I've posted this question to VHDL board, please forgive me if you've seen it there. Just thought it could be Quartus related so repost it here again.  I'm using Quartus 16 lite to create a simple interface between FT2232H and DE0-Nano in synchronous FIFO mode.  Please see simplified code below.   library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; --use IEEE.STD_LOGIC_UNSIGNED.all; -- for some old compiler use IEEE.MATH_REAL.all; library altera; use altera.altera_primitives_components.all; entity Tester is port( --DE0-Nano signal/pin definition ); end entity COMPONENT PLL IS PORT ( --- ); END COMPONENT; COMPONENT FIFO IS PORT ( --- ); END COMPONENT; COMPONENT Counter IS PORT ( --- ); END COMPONENT; ARCHITECTURE SYN OF Tester IS signal in_aclr, PLL_areset: STD_LOGIC; signal fast_clk, FT2232_clk: STD_LOGIC ; --PLL clock and FT2232H Sync FIFO mode clock signal nRXF, nTXE, nWR, nRD, nOE: STD_LOGIC; -- FT2232H interface signals signal FT_DataBus, iBusData_IN,iBusData_OUT, iData : STD_LOGIC_VECTOR (7 DOWNTO 0); --Databus and its derivatives signal ........................ -- other signal begin PLL_areset <= not GPIO_2_IN(0); in_aclr <= GPIO_2_IN(0) and iPLL_locked; FT2232_clk <= GPIO_0_IN(0); nRXF <= GPIO_0(5); nTXE <= GPIO_0(7); GPIO_0(3) <= nWR; GPIO_0(1) <= nRD; GPIO_0(0) <= nOE; FT_DataBus <= (GPIO_0(8), GPIO_0(9), GPIO_0(10), GPIO_0(11),GPIO_0(12),GPIO_0(13),GPIO_0(14), GPIO_0(15)); -- process (nOE) -- begin -- if nOE = '0' then -- iBusData_IN <= FT_DataBus; -- FT_DataBus <= (others => 'Z'); -- else ---- iBusData_IN <= (others => '0'); -- FT_DataBus <= iBusData_OUT; -- end if; -- -- end process; Process (in_aclr, FT2232_clk) begin if in_aclr = '0' then iBusData_IN <= (others => '0'); elsif rising_edge(FT2232_clk) then iBusData_IN <= FT_DataBus; end if; end process; FT_DataBus <= iBusData_OUT when nOE ='1' else (others => 'Z'); -------- Mapping components ---------   When I tried to compile it, I got these error message "Error (13066): Illegal directional connection from the pin "GPIO_0[8]" to the node "iBusData_IN[7]" for all 8 bits.  Searched around and tried a few methods but never solve it. Can't figure out why? Is it because some new development of VHDL I'm not aware or just the Quartus' interpretation? Since it should be very simple and straight forward, seems Quarts doesn't like me to use inout pin the feed a internal logic cell, but the bidir has to be supported because it's one of fundamental design units. Maybe I misunderstand either VHDL or Quartus error message ( humbly thinking altera could make the message more clear).  Anyway, please help and your help is appreciated in advance.  Thanks, Yu

[Altera_Forum]

Ive deleted your duplicate post, double posting is not allowed. 

 FPGAs only have tristates on the external pins. You cannot drive tri-states internally on the FPGA. hence the error.

[Altera_Forum]

--- Quote Start ---  Ive deleted your duplicate post, double posting is not allowed.  FPGAs only have tristates on the external pins. You cannot drive tri-states internally on the FPGA. hence the error.  --- Quote End ---    Hi, Tricky, Thanks a lot for your reply. I understand the FPGA can only drive tristate on the external pins and didn't mean to do it either.  In the below code, I was trying to latch the data from pin to internal register and put the internal data to pin when OE is enabled. Please help point out my misunderstanding. Appreciate it.  regards, Yu   Process (in_aclr, FT2232_clk) begin if in_aclr = '0' then iBusData_IN <= (others => '0'); elsif rising_edge(FT2232_clk) then iBusData_IN <= FT_DataBus; end if; end process; FT_DataBus <= iBusData_OUT when nOE ='1' else (others => 'Z');

[Altera_Forum]

That would be fine, but you're also driving FT_dataBus (an internal signal) here: 

 FT_DataBus <= (GPIO_0(8), GPIO_0(9), GPIO_0(10), GPIO_0(11),GPIO_0(12),GPIO_0(13),GPIO_0(14), GPIO_0(15));

[Altera_Forum]

Hi, Tricky, 

Thanks for pointing it out. I solved it now. Here is my code, put it below for people who're using the development module and keeping the old pin definition. Hope it can help. regards, Yu  ................. signal iBusData_IN,iBusData_OUT, iData : STD_LOGIC_VECTOR (7 DOWNTO 0); signal tmp_iBusData_IN,tmp_iBusData_OUT: STD_LOGIC_VECTOR (7 DOWNTO 0); ................... Process (in_aclr, FT2232_clk) begin if in_aclr = '0' then tmp_iBusData_IN <= (others => '0'); tmp_iBusData_OUT <= (others => '0'); elsif rising_edge(FT2232_clk) then tmp_iBusData_IN <= GPIO_0(15 downto 8); tmp_iBusData_OUT <= FIFO_q; end if; end process; ---------- Arrange range to fitGPIO_0(8 to 15) Reverse_bits: for i in iBusData_IN'range generate iBusData_IN(i) <= tmp_iBusData_IN (iBusData_IN'high -i); iBusData_OUT(i)<= tmp_iBusData_OUT (iBusData_IN'high -i); end generate; GPIO_0(15 downto 8) <= iBusData_OUT when nOE ='1' else (others => 'Z');