Quartus II compilation error message for pll clock fan out

Altera_Forum · ‎07-13-2016

Hi,

I'm working on a design. After compilation, I got a message as below.

Error: Net "enet_refclk_125MHz", which fans out to "test_clk_1", cannot be assigned more than one value

Error: Net is fed by "altlvds_tx_top:altlvds_tx_top|tx_coreclock"

Error: Net is fed by "pll_125:pll_125|c0"

This is a message for the pll clock fan out. How to fix it?

Thanks you.

Peter

Altera_Forum · ‎07-13-2016

It seems that you have fed your clock from two different sources. Feed it by one source or use a clock control core for supplying it with several clocks.

Altera_Forum · ‎07-13-2016

Hi msj,

Thanks for your answer. After receiving your comment, I've tried to check my code,

there was an error that I connected enet_refclk_125MHz to an output port of anther

module too. The message was misleading me to a problem of the clock fan outs.

It is solved now.

Thank you!

Peter Chang