I’m currently using Synplify FPGA flow to synthesis a design coded in RTL and pass the resulting netlist to Quartus to perform place and route, timing analysis and bitstream generation.
Synplify flow works okay but Quartus fails to route the the design, I’ve shown the error message I’m getting from Quartus in quartus_error.png. It should be straightforward for Quartus to fix the routing issues by inserting duplicate registers during the P&R stage but it doesn’t. I’ve set the following in Quartus but they have no effect:
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
set_global_assignment -name ROUTER_REGISTER_DUPLICATION ON
I’ve tried other seettings such as modifying the fitter seed but they don’t have any impact.
Any recommendations as to what I can do to resolve this issue?
Looks like we have found a workaround to the register duplication issue. In RTL I can insert synthesis commands to limit the max fanout on the registers that have fanout issues:
The number of additional registers that are inserted is minimal and there is little or no impact on utilization