Quartus Logic Lock flow

[GDeXi]

i'm learning Quartus User Guide like Bolck Based Design and PR. all of them are mention of Logic Lock.But I don't find any User Guide about Logic Lock(such as Quartus User Guide : Logic Lock).I don't understand how to plan Logic lock and how to use it correctly that improve my design performance.

could you help where is some user guide about how to use logic lock

[sstrell]

There's no user guide dedicated exclusively to Logic Lock. It's a feature that is part of other design flows so it is described in the user guides where needed. Floorplanning a design well is something of an art and learned from experience. But to get started, it depends on what you're trying to. If you are indeed going to be using partial reconfiguration (or any block-based flow), I'd recommend starting by compiling the full design (for PR, this is the base compile) with no Logic Lock regions set. Then, using cross-probing and the reporting features in the Chip Planner, see where the logic you need to isolate gets placed by the Fitter. Create an LL region for the PR region logic (and for PR, a related routing region) in about the same area, making it a bit larger than what you might think you need to allow for the boundary LUTs required for PR and for room to grow in the future. Recompile and see how you did, making sure to perform a timing analysis to make sure your design still meets performance requirements (very very important for the PR flow).

This flow for the use of LL regions is also good if you just want to use incremental block-based compilation or design block reuse. See what the Fitter chooses on its own first and then create a floorplan similar to what you get from the tool.

#iwork4intel

[GDeXi]

I seem to have grasped some key points. See what the Fitter chooses on its own first and then create a floorplan similar to what you get from the tool. I'm new to Quartus, in other words, I'm a beginner on FPGA. Thanks for your help.

[Kenny_Tan]

Additional, for root partition logic lock. You will need to pull most of your periphery logic to the top level and lock from there. you can refer to https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/tt/tt-intel-fpga-design-reuse.pdf for root partition logic lock.

You can use the default Auto size and Floating location LogicLock region properties to estimate the preliminary size and location for the PR region as well.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/qts/qts_qii51026.pdf page 4-18

[GDeXi]

Thanks,i will read this Doc  and learn it