Quartus complain about LVDS pin assignment for MAX V CPLD device

[TChin5]

I have two signal "OUT_P" and "OUT_N" that I try to assign using Pin Planner with I/O standard lvds_e_r3. I try this many ways and Quartus v17.1.0 returns errors. I assigned them to D15/C14 in Bank 2 which are the P/N pair. Bank2 is set to 2.5v and it only has these two signals.

I check the web and try out many techniques but none of them work.

I try commenting the "OUT_N" signal in my VHDL file and only assigned LVDS to OUT_P as LVDS_E_3R. This allow Pin Planner to automatically create OUT_P(N). But again during Compile I got a "Quartus Problem Report" popup window during the FITTER process.

How can I assigned them properly.

[Abe]

Thats the worng way of going about LVDS. To work with LVDS signals, you need not generate both _n and _p signals in your VHDL code. The logic will be single-ended only, ie , you will have only the OUT signal as single-ended from your logic.

To get LVDS signals, you just assign the OUT signal to an LVDS IO pin and change the IO Standard to LVDS. The Pin planner will automatically assign the OUT_n pin to the next adjacent LVDS pair for that pin.

[Abe]

Post the project archive here.. we can take a look at it and help. Try installing latest version of Quartus.