I am trying to compile my design with TSE MAC. I could see a fitter error from quartus which seems to be from internal PLL in one of the IP. Can you kindly help?
Note that the same design is working fine with 17.1 prime.
Thanks for submitting the issue.
Please do let me have some time to investigate on your case and I will get back to you with findings.
Since I have addressed your question and didn't hear any feedback from you, I am now close the case. If you still have any question after the closed case, please do feel free to submit another issue.