Re: Quartus13.1 Fatal Error, when generate .sof

Altera_Forum · ‎03-29-2018

Hi,

I compile the project, the quartus shows it already pass synthesis and fitter successfully,

the error shows when generate programming files, error message is show as follow:

the quartus versions I use is 13.1 and FPGA is 5CGXFC7D6

anyone knows what's the reason cause this problem and how to solve it?

Thanks in advance.

Qi

Altera_Forum · ‎03-29-2018

Hi,

Can you tell about your design?

The error may be because of logical issues.

Or

Try a different version of Quartus.

Best Regards,

Anand Raj Shankar

(This message was posted on behalf of Intel Corporation)

Altera_Forum · ‎03-29-2018

this project is:

1. transmit 8 channels lvds signals (200M) out to daugther board, use ALTLVDS_TX ipcore;

2. receive 8 channels lvds signals (200M) in from daugther board, use oversampling logic;

3. collecting 8 channels data and transmit to PC by cameralink;

4. other modules all some data processing;

is this enough?

Altera_Forum · ‎03-29-2018

Try deleting the db and incremental_db directories and then recompiling. Something could just be corrupted.